Device and method for reducing contact resistance of a metal

• US 10,276,431 B2
• Filed: 02/12/2018
• Issued: 04/30/2019
• Est. Priority Date: 07/31/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Ya-Lien, Su, Hung-Wen, Lee, Kuei-Pin, Lin, Yu-Hung, Chang, Yu-Min
• Primary Examiner(s): Moore, Whitney
• Application Number:
  US15/894,051
• Publication Number:
  US 20180174898A1
• Time in Patent Office: 442 Days
• Field of Search: None
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (CVD) TaN layer formed on a side wall of the trench; a physical vapor deposition (PVD) Ta layer formed over the CVD TaN layer; and a metal-containing layer formed over the PVD Ta layer.

Claims

1. A device, comprising:

a semiconductor substrate;

a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and

a structure in the trench, wherein the structure includes;

a chemical vapor deposition (CVD) TaN layer formed on a side wall of the trench;

a physical vapor deposition (PVD) Ta layer formed over the CVD TaN layer; and

a metal-containing layer formed over the PVD Ta layer;

wherein the structure further includes a PVD TaN layer between the CVD TaN layer and the PVD Ta layer.

2. The device of claim 1, further comprising a cap layer between the semiconductor substrate and the dielectric layer, wherein the cap layer includes silicon nitride.

3. The device of claim 1, wherein a carbon content in the PVD TaN layer and the PVD Ta layer is lower than about 0.2%.

4. The device of claim 1, wherein a nitrogen to tantalum ratio in the PVD TaN layer ranges from about 0.3 to about 0.6.

5. The device of claim 1, wherein the metal-containing layer includes copper.

6. A device, comprising:

a semiconductor substrate;

a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and

a structure embedded in the trench, wherein the structure includes;

a first TaN layer formed on bottom and side walls of the trench;

a physical vapor deposition (PVD) Ta layer formed over the first TaN layer; and

a metal-containing layer formed over the PVD Ta layer, wherein the first TaN layer has a nitrogen to tantalum ratio (N/Ta) greater than 1;

wherein the structure further includes a PVD TaN layer between the first TaN layer and the PVD Ta layer.

7. The device of claim 6, wherein the first TaN layer is deposited using atomic layer deposition (ALD), and the N/Ta ratio in the first TaN layer ranges from about 2.3 to about 2.6.

8. The device of claim 7, wherein a carbon content in the first TaN layer and the PVD Ta layer ranges from about 0.2% to about 1%.

9. The device of claim 6, wherein the first TaN layer has a thickness ranging from about 5 to about 10 angstrom (Å

).

10. The device of claim 6, wherein an overall N/Ta ratio of the first TaN layer and the PVD Ta layer ranges from about 0.6 to about 1.0.

11. The device of claim 6, wherein the metal-containing layer includes copper.

12. The device of claim 6, wherein an overall N/Ta ratio of the first TaN layer, the PVD Ta layer, and the PVD TaN layer ranges from about 0.6 to about 1.0.

13. The device of claim 6, wherein a carbon content in the first TaN layer, the PVD Ta layer, and the PVD TaN layer ranges from about 0.2% to about 1%.

14. A device, comprising:

a semiconductor substrate;

a cap layer having silicon nitride deposited over the semiconductor substrate;

a dielectric layer deposited over the cap layer; and

a first structure penetrating the dielectric layer and the cap layer, wherein the first structure includes;

a first TaN layer on bottom and side walls of the first structure, wherein the first TaN layer is deposited using either atomic layer deposition (ALD) or chemical vapor deposition (CVD);

a physical vapor deposition (PVD) Ta layer over the first TaN layer; and

a metal-containing layer over the PVD Ta layer;

wherein the first structure further includes a PVD TaN layer between the first TaN layer and the PVD Ta layer.

15. The device of claim 14, wherein a nitrogen to tantalum ratio of the first TaN layer and the PVD Ta layer ranges from about 0.6 to about 1.0, and a carbon content in the first TaN layer and the PVD Ta layer ranges from about 0.2% to about 1%.

16. The device of claim 14, wherein the metal-containing layer is in direct contact with the PVD Ta layer and includes copper.

17. The device of claim 14, further comprising:

a second structure disposed directly on the first structure, wherein the second structure includes a PVD TaN layer on bottom and side walls of the second structure, and another PVD Ta layer on the PVD TaN layer.

18. The device of claim 14, wherein a carbon content in the PVD TaN layer and the PVD Ta layer is lower than about 0.2%.

19. The device of claim 14, wherein a nitrogen to tantalum ratio in the PVD TaN layer ranges from about 0.3 to about 0.6.

20. The device of claim 14, wherein a carbon content in the first TaN layer, the PVD Ta layer, and the PVD TaN layer ranges from about 0.2% to about 1%, and wherein a nitrogen to tantalum ratio in the PVD TaN layer ranges from about 0.6 to about 1.0.