Method of adjusting signal to noise ratio of SRAM and invertor structure

• US 10,276,446 B1
• Filed: 05/10/2018
• Issued: 04/30/2019
• Est. Priority Date: 04/13/2018
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Lee, Wei-Chi, Wang, Han-Tsun, Chen, Chang-Hung, Yang, Po-Yu, Fan, Mei-Ying, Tsai, Mu-Kai, Lin, Guan-Shyan, Kuo, Tsz-Hui, Chen, Cheng-Hsiung
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US15/976,848
• Time in Patent Office: 355 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

Claims

1. An inverter structure comprising:

a substrate comprising a P-type transistor region and an N-type transistor region;

a first fin structure disposed within the P-type transistor region;

a second fin structure disposed within the N-type transistor region, wherein the first fin structure and the second fin structure are parallel;

a gate line disposed within the P-type transistor region and the N-type transistor region, the gate line being perpendicular to the first fin structure, wherein the gate line comprises a first end within the P-type transistor region and a second end within the N-type transistor region; and

two first dummy gate lines respectively disposed at two sides of the gate line, the two first dummy gate lines being perpendicular to the first fin structure, wherein each of the first dummy gate lines comprises a third end within the P-type transistor region and a fourth end within the N-type transistor region;

wherein a first distance between the first end and the first fin structure is greater than a third distance between the third end and the first fin structure, and a second distance between the second end and the second fin structure is smaller than a fourth distance between the fourth end and the second fin structure.

2. The inverter structure of claim 1, further comprising two second dummy gate lines, wherein each of the two second dummy gate lines is respectively disposed at one side of each of the two first dummy gate lines, and is not between one of the two first dummy gate lines and the gate line, each of two second dummy gate lines comprises a fifth end within the P-type transistor region and a sixth end within the N-type transistor region, the third distance is greater than a fifth distance between the fifth end and the first fin structure, and the fourth distance is smaller than a sixth distance between the sixth end and the second fin structure.

3. The inverter structure of claim 1, wherein the first distance, the second distance, the third distance, and the fourth distance are parallel to the gate line.

4. The inverter structure of claim 1, wherein an overlapped region of the gate line and the first fin structure forms a P-type gate, and two P-type doped regions are respectively disposed in the first fin structure at two sides of the P-type gate.

5. The inverter structure of claim 1, wherein an overlapped region of the gate line and the second fin structure forms an N-type gate, and two N-type doped regions are respectively disposed in the second fin structure at two sides of the N-type gate.

6. The inverter structure of claim 1, wherein the first end, the second end, the third end and the fourth end are respectively encapsulated by a dielectric layer.