Semiconductor device and manufacturing method thereof

• US 10,276,572 B2
• Filed: 11/05/2015
• Issued: 04/30/2019
• Est. Priority Date: 11/05/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Fung, Ka-Hing
• Primary Examiner(s): Hossain, Moazzam
• Assistant Examiner(s): Mojaddedi, Omar F
• Application Number:
  US14/933,885
• Publication Number:
  US 20170133375A1
• Time in Patent Office: 1,272 Days
• Field of Search: 257369, 257288
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device includes a first channel region disposed over a substrate, a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region, a gate dielectric layer disposed on and wrapping the first channel region, a gate electrode layer disposed on the gate dielectric layer and wrapping the first channel region, and a second source region and a second drain region disposed over the substrate and below the first source region and the first drain region, respectively. The second source region and the second drain region are in contact with the gate dielectric layer. A lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region.

Claims

1. A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET comprising:

a first channel region disposed over a substrate;

a first source region and a first drain region disposed over the substrate and connected to the first channel region such that the first channel region is disposed between the first source region and the first drain region along a first direction;

a gate dielectric layer disposed on the first channel region;

a gate electrode layer disposed on the gate dielectric layer; and

a second source region and a second drain region disposed over the substrate wherein;

the second source region and the second drain region are in contact with the gate dielectric layer,

a lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region, and

when viewed in a cross section perpendicular to the first direction, the first source region completely surrounds the second source region, and the first drain region completely surrounds the second drain region.

2. The semiconductor device of claim 1, wherein:

a space is provided between the first channel region and the substrate in a vertical direction perpendicular to a surface of the substrate and between the second source region and the second drain region in a horizontal direction parallel to the surface of the substrate, and

the space is filled with the gate dielectric layer and the gate electrode.

3. The semiconductor device of claim 1, wherein:

the first channel region is made of Si or a Si-based compound, and

the first source region and the first drain region are made of Ge or SiGe.

4. The semiconductor device of claim 3, wherein:

the second source region and the second drain region are made of SiGe, and

a Ge content of the second source region and the second drain region is smaller than a Ge content of the first source region and the first drain region.

5. The semiconductor device of claim 1, the GAA-FET further comprises:

a second channel region disposed over the first channel region with a space filled with the gate dielectric layer and the gate electrode, the gate dielectric layer and the gate electrode being disposed over the second channel region;

a third source region disposed over the first source region, and a third drain region disposed over the first drain region;

a fourth source region disposed over the third source region and connected to the second channel region; and

a fourth drain region disposed over the third source region and connected to the second channel region such that the second channel region is disposed between the fourth source region and the fourth drain region,

wherein a lattice constant of the third source region and the third drain region is different from a lattice constant of the fourth source region and the fourth drain region.

6. The semiconductor device of claim 5, wherein:

the first and second channel regions are made of Si or a Si-based compound, and

the first and fourth source regions and the first and fourth drain regions are made of Ge or SiGe.

7. The semiconductor device of claim 6, wherein:

the second and third source regions and the second and third drain regions are made of SiGe, and

a Ge content of the second and third source regions and the second and third drain regions is smaller than a Ge content of the first and fourth source regions and the first and fourth drain regions.

8. A semiconductor device, comprising a p-channel gate-all-around field effect transistor (p-GAA FET) and an n-channel gate-all-around around field effect transistor (n-GAA FET), wherein:

each of the p-GAA FET and the n-GAA-FET comprises;

a fin structure disposed over a substrate;

a gate structure partially covering the fin structure; and

a source and drain (S/D) structure formed over the fin structure not covered by the gate structure,

the gate structure of each of the p-GAA FET and the n-GAA-FET includes;

a first channel region disposed over the substrate and extending in a first direction;

a gate dielectric layer disposed on the first channel region; and

a gate electrode layer disposed on the gate dielectric layer, and in the p-GAA FET;

the S/D structure includes a first S/D layer and a second S/D layer having a different lattice constant from the first S/D layer,

the first S/D layer is connected to the first channel region along the first direction,

the first S/D layer has a different lattice constant than the first channel region,

a side face of the second S/D layer is in contact with the gate dielectric layer, and

the second S/D layer includes a second source region and the first S/D layer includes a first source region completely surrounding the second source region when viewed in a cross section perpendicular to the first direction.

9. The semiconductor device of claim 8, wherein:

the first channel regions are made of Si or a Si-based compound, and

the first S/D layer is made of Ge or SiGe.

10. The semiconductor device of claim 9, wherein:

the second S/D layer are made of SiGe, and

a Ge content of the first S/D layer is greater than a Ge content of the second S/D layer.

11. The semiconductor device of claim 8, wherein multiple first channel regions and corresponding multiple first S/D layers are provided in a vertical direction.

12. The semiconductor device of claim 8, wherein, in the n-GAA-FET:

the S/D structure includes a third S/D layer,

the third S/D layer is connected to the first channel region, and

the third S/D layer has a different lattice constant than the first channel region.

13. The semiconductor device of claim 8, wherein, in the n-GAA-FET, the S/D structure includes no layered structure.

14. A semiconductor device including a gate-all-around field effect transistor (GAA FET), the GAA FET, comprising:

a first channel region disposed over a substrate;

a second channel region disposed over the substrate at a different height than the first channel region;

a first source region and a first drain region disposed over the substrate and connected to the first channel region and the second channel region such that, along a first direction, the first channel region is disposed between the first source region and the first drain region and the second channel region is disposed between the first source region and the first drain region;

a gate dielectric layer disposed on the first channel region;

a gate electrode layer disposed on the gate dielectric layer; and

a second source region and a second drain region disposed over the substrate, wherein;

the second source region and the second drain region are in contact with the gate dielectric layer,

a lattice constant of the first source region and the first drain region is different from a lattice constant of the second source region and the second drain region, and

when viewed in a cross section perpendicular to the first direction, the first source region completely surrounds the second source region, and the first drain region completely surrounds the second drain region.

15. The semiconductor device of claim 14, wherein the first source region wraps around the second source region, and the first drain region wraps around and contacts the second drain region.

16. The semiconductor device of claim 14, wherein:

a space is provided between the first channel region and the substrate in a vertical direction perpendicular to a surface of the substrate and between the second source region and the second drain region in a horizontal direction parallel to the surface of the substrate, and

the space is filled with the gate dielectric layer and the gate electrode.

17. The semiconductor device of claim 14, wherein:

the first channel region is made of Si or a Si-based compound, and

the first source region and the first drain region are made of Ge or SiGe.

18. The semiconductor device of claim 17, wherein:

the second source region and the second drain region are made of SiGe, and

a Ge content of the second source region and the second drain region is smaller than a Ge content of the first source region and the first drain region.

19. The semiconductor device of claim 14, further comprising a third source region and a third drain region disposed on the substrate, and made of a same material as the second source region and the second drain region.

20. The semiconductor device of claim 19, wherein the third source region is sandwiched by the first source region and the substrate and the third drain region is sandwiched by the first drain region and the substrate.