High coupling ratio split gate memory cell

• US 10,276,582 B2
• Filed: 08/21/2017
• Issued: 04/30/2019
• Est. Priority Date: 08/21/2017
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: Sun, Yuan, Tan, Shyue Seng, Toh, Eng Huat
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US15/681,442
• Publication Number:
  US 20190057970A1
• Time in Patent Office: 617 Days
• Field of Search: 36518526, 36518524
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A split gate non-volatile memory (NVM) cell formed on a crystalline-on-insulator (COI) substrate, such as a fully or partially depleted silicon-on-insulator (SOI) substrate is disclosed. The split gate memory cell includes a split gate disposed on a surface substrate of the SOI substrate between source/drain (S/D) regions. The split gate includes a storage gate with a control gate (CG) over a floating gate (FG), and a select gate (SG). A back gate is provided on the bulk substrate below a buried oxide (BOX). The back gate may be doped with the same polarity type dopants as the S/D regions. The back gate is coupled to the CG to increase CG coupling ratio, improving programming performance. Alternatively, the back gate may be doped with the opposite polarity type dopants as the S/D regions. The back gate is coupled to a negative bias during program and erase operations. The negative bias increases the gate threshold voltages of the SG and CG, resulting in higher electron generation efficiency to improve programming speed as well as a higher electric field to increase erase speed.

Claims

1. A non-volatile memory (NVM) cell, comprising

a substrate, the substrate including a surface substrate and a bulk substrate separated by an insulator layer;

a split gate transistor disposed on the substrate, the split gate transistor including a first gate and a second gate separated by an intergate dielectric; and

a back gate in a surface portion of the bulk substrate adjacent to the insulator layer, the back gate serving as a back gate terminal of the NVM cell and coupled to back gate bias voltage (V_BG).

2. The device of claim 1, wherein the insulator layer is an ultra-thin buried oxide (UTBOX).

3. The device of claim 2, wherein the first gate serves as a storage gate and includes a first storage gate disposed underneath a second storage gate.

4. The device of claim 3, wherein the first storage gate is a floating gate (FG) and the second storage gate is a control gate (CG), the FG includes a FG electrode disposed over a FG dielectric, and the CG includes a CG electrode disposed over a CG dielectric.

5. The device of claim 4, wherein the CG dielectric is an oxide-nitride-oxide (ONO) stack.

6. The device of claim 3, wherein the second gate serves as a select gate (SG), and the SG includes a SG electrode disposed over a SG dielectric.

7. The device of claim 6, wherein the bulk substrate includes an isolation well which isolates the back gate from the bulk substrate and has a greater depth than the back gate.

8. A method of forming a non-volatile memory (NVM) cell, comprising:

providing a substrate, the substrate includes a surface substrate and a bulk substrate separated by an insulator layer;

forming a split gate transistor disposed on the substrate, wherein forming the split gate transistor includes forming a first gate adjacent to a second gate and separated by an intergate dielectric; and

forming a back gate in a surface portion of the bulk substrate adjacent to the insulator layer, wherein the back gate serves as a back gate terminal of the NVM cell and is coupled to back gate bias voltage (V_BG).

9. The method of claim 8, wherein the insulator layer is an ultra-thin buried oxide (UTBOX).

10. The method of claim 9, wherein the first gate serves as a storage gate, and forming the first gate includes disposing a second storage gate over a first storage gate, the first storage gate serves as a floating gate (FG), and the second storage gate serves as a control gate (CG).

11. The method of claim 10, wherein forming the FG includes disposing a FG electrode over a FG dielectric, and forming the CG includes disposing a CG electrode over a CG dielectric.

12. The method of claim 11, wherein the CG dielectric is an oxide-nitride-oxide (ONO) stack.

13. The method of claim 10, wherein the second gate serves as a select gate (SG), and forming the SG includes disposing a SG electrode over a SG dielectric.

14. The method of claim 13, wherein the bulk substrate includes an isolation well which isolates the back gate from the bulk substrate and has a greater depth than the back gate.

15. A device comprising:

a substrate, the substrate includes a surface substrate and a bulk substrate separated by an insulator layer;

a plurality of non-volatile memory (NVM) cells on and in the substrate, the NVM cells interconnected in a row direction and a column direction to form a memory array with rows and columns of the NVM cells, wherein each of the NVM cell includes;

a split gate transistor disposed on the substrate, the split gate transistor disposed between first and second source/drain (S/D) regions, wherein the split gate transistor includes a select gate (SG) and a storage gate separated by an intergate dielectric, and

a back gate in a surface portion of the bulk substrate adjacent to the insulator layer, wherein the back gate serves as a back gate terminal of the NVM cells and is coupled to back gate bias voltage (V_BG);

the NVM cells od each row are interconnected by a control gate line (CGL) coupled to control gate (CG) terminals of a respective row of the NVM cells and a select gate line (SGL) coupled to select gate (SG) terminals of a respective row of the NVM cells; and

the NVM cells of each column are interconnected by a source line (SL) coupled to source terminals of a respective column of the NVM cells and a bitline (BL) coupled to drain terminals of a respective column of the NVM cells.

16. The device of claim 15, wherein the storage gate comprises:

a floating gate (FG), the FG including a FG electrode disposed over a FG dielectric; and

a CG, the CG including a CG electrode disposed over a CG dielectric, and wherein the CG is disposed over the FG, and the CG electrode serves as the CG terminal.

17. The device of claim 16, wherein the SG comprises a SG electrode disposed over a SG dielectric, and the SG electrode serves as the SG terminal.

18. The device of claim 15, wherein the first S/D region is a drain region and serves as a drain terminal, and the second S/D region is a source region and serves as a source terminal.

19. The device of claim 15, wherein the bulk substrate comprises an isolation well which isolates the back gate from the bulk substrate and has a greater depth than the back gate.

20. A device comprising:

a plurality of non-volatile memory (NVM) cells, wherein the NVM cells are interconnected in a row direction and a column direction to form a memory array with rows and columns of the NVM cells, and wherein the NVM cells are disposed in and on a substrate, the substrate includes a surface substrate and a bulk substrate separated by an insulator layer;

the NVM cells of each row are interconnected by a control gate line (CGL) coupled to control gate (CG) terminals of a respective row of the NVM cells and a select gate line (SGL) coupled to select gate (SG) terminals of a respective row of the NVM cells;

the NVM cells of each column are interconnected by a source line (SL) coupled to source terminals of a respective column of the NVM cells and a bitline (BL) coupled to drain terminals of a respective column of the NVM cells; and

each of the NVM cells includes a back gate coupled to its respective CGL.

21. The device of claim 20, wherein the insulator layer comprises an ultra-thin buried oxide (UTBOX).

22. The device of claim 20, wherein the back gate of each of the NVM cells comprises a doped well that is disposed in the bulk substrate.

23. The device of claim 22, wherein the back gate of each of the NVM cells in the row direction are commonly coupled to the CGL of the row.