Vertical memory device
First Claim
1. A vertical memory device comprising:
- a substrate having a cell array region and a connection region adjacent to the cell array region;
a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and the plurality of gate electrode layers form a stepped structure in the connection region;
at least one first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate; and
at least one second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate,wherein a depth of a lower end portion of the at least one second metal line is greater than a depth of a lower end portion of the at least one first metal line in the cell array region, based on an upper surface of the substrate.
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Abstract
A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.
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Citations
20 Claims
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1. A vertical memory device comprising:
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a substrate having a cell array region and a connection region adjacent to the cell array region; a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and the plurality of gate electrode layers form a stepped structure in the connection region; at least one first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate; and at least one second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate, wherein a depth of a lower end portion of the at least one second metal line is greater than a depth of a lower end portion of the at least one first metal line in the cell array region, based on an upper surface of the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A vertical memory device comprising:
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a substrate having a cell array region and a connection region located adjacent the cell array region; first and second recesses formed in an upper portion of the substrate, the first recess extending in a first direction in the cell array region and the connection region and the second recess being disposed in the connection region; a common source line disposed on the first recess; and a dummy source line disposed on the second recess, wherein a depth of the second recess is greater than a depth of the first recess of the cell array region, based on an upper surface of the substrate. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A vertical memory device comprising:
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a substrate having a cell array region and a connection region adjacent to the cell array region; a stacked structure including a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and extending to have different lengths in the connection region; a common source line dividing the stacked structure in the cell array region and the connection region; and a dummy source line dividing the stacked structure in the connection region, wherein a vertical length of the dummy source line is greater than a vertical length of the common source line.
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Specification