Vertical memory device

• US 10,276,591 B2
• Filed: 03/28/2018
• Issued: 04/30/2019
• Est. Priority Date: 07/21/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kwang Ho, Kim, Kwang Ho, Cho, Seung Hynu, Yu, Ji Hwan
• Primary Examiner(s): Nguyen, Niki H
• Application Number:
  US15/937,932
• Publication Number:
  US 20190027491A1
• Time in Patent Office: 398 Days
• Field of Search: 257314-326, 257E27078, 257E293-E29309, 257255-266, 257E21179-E21182, 257E21209-E2121, 257E21422, 257E21423, 257E21679-E21694
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

Claims

1. A vertical memory device comprising:

a substrate having a cell array region and a connection region adjacent to the cell array region;

a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and the plurality of gate electrode layers form a stepped structure in the connection region;

at least one first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate; and

at least one second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate,

wherein a depth of a lower end portion of the at least one second metal line is greater than a depth of a lower end portion of the at least one first metal line in the cell array region, based on an upper surface of the substrate.

2. The vertical memory device of claim 1, wherein the at least one second metal line extends in the same direction as a direction in which the at least one first metal line extends, and is disposed at an edge portion of the connection region.

3. The vertical memory device of claim 2, wherein a difference between a depth of a lower end portion of the at least one second metal line, and a depth of a lower end portion of the at least one first metal line in the cell array region is about 15 nm or more.

4. The vertical memory device of claim 1, wherein a height from the upper surface of the substrate to an upper surface of an uppermost gate electrode layer among the plurality of gate electrode layers is about 4.4 μ

m or more.

5. The vertical memory device of claim 1, wherein the at least one second metal line extends in a direction intersecting the at least one first metal line, and has a length shorter than a length of the at least one first metal line.

6. The vertical memory device of claim 5, wherein the at least one second metal line comprises a plurality of second metal lines, and a depth of the lower end portion of each of the second metal lines is increased relative to a respective position toward an edge of the connection region.

7. The vertical memory device of claim 1, wherein the at least one first metal line comprises a plurality of first metal lines, and the depth of the lower end portion of each of the first metal lines is increased relative to a respective position toward an edge of the connection region.

8. The vertical memory device of claim 7, wherein a difference between a depth of the lower end portion of the first metal lines in the cell array region and a depth of the lower end portion of the first metal lines at an edge portion of the connection region is about 15 nm or more.

9. The vertical memory device of claim 1, wherein the at least one second metal line comprises a plurality of second metal lines extending in the same direction as a direction in which the first metal line extends, and having a length shorter than a length of the first metal line.

10. The vertical memory device of claim 1, wherein the at least one second metal line comprises a plurality of second metal lines, and the at least one first metal line comprises a plurality of first metal lines, and wherein the second metal lines comprise portions having different line widths.

11. The vertical memory device of claim 1, further comprising channel structures disposed in the cell array region, extending in a direction perpendicular to the upper surface of the substrate, and penetrating through the plurality of gate electrode layers.

12. The vertical memory device of claim 11, further comprising dummy channel structures disposed in the connection region, extending in the same direction as a direction in which the channel structures extend, and the dummy channel structures penetrating through at least a portion of the plurality of gate electrode layers.

13. The vertical memory device of claim 12, wherein the channel structures and the dummy channel structures have the same or a similar structure.

14. A vertical memory device comprising:

a substrate having a cell array region and a connection region located adjacent the cell array region;

first and second recesses formed in an upper portion of the substrate, the first recess extending in a first direction in the cell array region and the connection region and the second recess being disposed in the connection region;

a common source line disposed on the first recess; and

a dummy source line disposed on the second recess,

wherein a depth of the second recess is greater than a depth of the first recess of the cell array region, based on an upper surface of the substrate.

15. The vertical memory device of claim 14, wherein the dummy source line and the second recess extend in the first direction, and the second recess is located at an edge portion of the connection region;

and

the depth of the second recess is about 15 nm or more greater than the depth of the first recess of the cell array region.

16. The vertical memory device of claim 14, wherein the dummy source line and the second recess extend in a second direction intersecting the first direction, and the depth of the second recess is increased toward an edge of the connection region.

17. The vertical memory device of claim 16, wherein the depth of the second recess at an edge portion of the connection region is about 15 nm or more greater than the depth of the first recess in the cell array region.

18. The vertical memory device of claim 14, wherein the depth of the first recess is increased toward an edge of the connection region in the connection region.

19. The vertical memory device of claim 18, wherein the depth of the first recess at an edge portion of the connection region is about 15 nm or more greater than the depth of the first recess in the cell array region.

20. A vertical memory device comprising:

a substrate having a cell array region and a connection region adjacent to the cell array region;

a stacked structure including a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and extending to have different lengths in the connection region;

a common source line dividing the stacked structure in the cell array region and the connection region; and

a dummy source line dividing the stacked structure in the connection region,

wherein a vertical length of the dummy source line is greater than a vertical length of the common source line.