Display device and electronic device

• US 10,276,594 B2
• Filed: 09/07/2017
• Issued: 04/30/2019
• Est. Priority Date: 09/12/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koezuka, Junichi, Okazaki, Kenichi
• Primary Examiner(s): Harriston, William A
• Application Number:
  US15/698,117
• Publication Number:
  US 20180076231A1
• Time in Patent Office: 600 Days
• Field of Search: None
• CPC Class Codes: G09G 2320/103 Detection of image changes, e.g. determination of an index representative of the image change
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2330/04 Display protection
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2360/144 the light being ambient light
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A novel display device is provided. The display device includes a pixel portion and a driver circuit for driving the pixel portion. The driver circuit includes a first transistor having a dual-gate structure. The pixel portion includes a second transistor having a single-gate structure and a pixel electrode electrically connected to the second transistor. The first transistor and the second transistor each include a first metal oxide film functioning as a channel. The metal oxide films each include a first region and a second region. The first region contains In or Zn, and oxygen. The second region contains In or an element M, and oxygen. The first region and the second region are dispersed or distributed in a mosaic pattern.

Claims

1. A display device comprising:

a pixel portion; and

a driver circuit for driving the pixel portion,

wherein the driver circuit comprises a first transistor,

wherein the pixel portion comprises a second transistor and a pixel electrode electrically connected to the second transistor,

wherein the first transistor comprises a first gate electrode, a first metal oxide film serving as a channel over the first gate electrode and a second gate electrode over the first metal oxide film,

wherein the first gate electrode and the second gate electrode are electrically connected to each other,

wherein the second transistor comprises a second metal oxide film serving as a channel,

wherein the pixel electrode comprises a third metal oxide film,

wherein the third metal oxide film comprises a region having higher hydrogen concentration than the second metal oxide film,

wherein the first metal oxide film, the second metal oxide film, and the third metal oxide film each comprise In, Zn, and an element M,

wherein the first metal oxide film, the second metal oxide film, and the third metal oxide film each comprise a plurality of first regions and a plurality of second regions,

wherein the plurality of first regions comprise In or Zn, and oxygen,

wherein the plurality of second regions comprise In or the element M, and oxygen, and

wherein the plurality of first regions and the plurality of second regions are mixed so as to be dispersed or distributed in a mosaic pattern.

2. The display device according to claim 1,

wherein an insulating film is over the first metal oxide film and the second transistor,

wherein the second metal oxide film is over a gate insulating film,

wherein the third metal oxide film and the second gate electrode are over the insulating film, and

wherein the third metal oxide film is electrically connected to the second transistor in an opening of the insulating film.

3. The display device according to claim 1,

wherein a first insulating film and a second insulating film are stacked in this order over the second transistor,

wherein the first insulating film is over the first metal oxide film,

wherein the first insulating film and the second insulating film each have an opening over the second transistor,

wherein the second metal oxide film is over a gate insulating film,

wherein the second gate electrode is over the first insulating film,

wherein the third metal oxide film is over the second insulating film, and

wherein the third metal oxide film is electrically connected to the second transistor in the openings of the first insulating film and the second insulating film.

4. The display device according to claim 3,

wherein the first insulating film comprises an inorganic insulating film, and

wherein the second insulating film comprises an organic resin film.

5. The display device according to claim 1,

wherein the second transistor comprises a third gate electrode and a gate insulating film between the third gate electrode and the second metal oxide film, and

wherein the second metal oxide film and the third metal oxide film are over the gate insulating film.

6. The display device according to claim 1, wherein a hydrogen concentration of the third metal oxide film is higher than or equal to 1×

10²⁰ atoms/cm³.

7. The display device according to claim 1,

wherein the first metal oxide film, the second metal oxide film, and the third metal oxide film each comprise a region where an In content accounts for 40% or higher and 50% or lower of a total sum of In, M, and Zn atoms and a region where an M content accounts for 5% or higher and 30% or lower of the total sum of In, M, and Zn atoms, and

wherein the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

8. The display device according to claim 1,

wherein an atomic ratio of In to M and Zn is 4:

x;

y in the first metal oxide film, the second metal oxide film, and the third metal oxide film, where x is greater than or equal to 1.5 and less than or equal to 2.5 and y is greater than or equal to 2 and less than or equal to 4, and

wherein the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

9. The display device according to claim 1,

wherein an atomic ratio of In to M and Zn is 5:

x;

y in the first metal oxide film, the second metal oxide film, and the third metal oxide film, where x is greater than or equal to 0.5 and less than or equal to 1.5 and y is greater than or equal to 5 and less than or equal to 7, and

wherein the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

10. The display device according to claim 1,

wherein the first transistor has a dual-gate structure, and

wherein the second transistor has a single-gate structure.

11. An electronic device comprising:

the display device according to claim 1; and

a receiver.

12. The display device according to claim 1,

wherein the plurality of the first regions each have a size of greater than or equal to 0.5 nm and less than or equal to 3 nm, and

wherein the plurality of the second regions each have a size of greater than or equal to 0.5 nm and less than or equal to 3 nm.

13. A display device comprising:

a pixel portion; and

a driver circuit for driving the pixel portion,

wherein the driver circuit comprises a first transistor,

wherein the pixel portion comprises a second transistor and a pixel electrode electrically connected to the second transistor,

wherein a first insulating film and a second insulating film are stacked in this order over the second transistor,

wherein the first insulating film and the second insulating film each have an opening over the second transistor,

wherein the first transistor comprises a first gate electrode, a first metal oxide film serving as a channel over the first gate electrode, the first insulating film over the first metal oxide film, and a second gate electrode over the first insulating film,

wherein the first gate electrode and the second gate electrode are electrically connected to each other,

wherein the second transistor comprises a second metal oxide film serving as a channel,

wherein the pixel electrode is over the second insulating film,

wherein the pixel electrode is electrically connected to the second transistor in the openings of the first insulating film and the second insulating film,

wherein the first metal oxide film and the second metal oxide film each comprise In, Zn, and an element M,

wherein the first metal oxide film and the second metal oxide film each comprise a plurality of first regions and a plurality of second regions,

wherein the plurality of first regions comprise In or Zn, and oxygen,

wherein the plurality of second regions comprise In or the element M, and oxygen, and

wherein the plurality of first regions and the plurality of second regions are mixed so as to be dispersed or distributed in a mosaic pattern.

14. The display device according to claim 13,

wherein the pixel electrode comprises a third metal oxide film,

wherein the third metal oxide film comprises In, Zn, and the element M, and

wherein the third metal oxide film comprises a region having higher hydrogen concentration than the second metal oxide film.

15. The display device according to claim 14, wherein a hydrogen concentration of the third metal oxide film is higher than or equal to 1×

10²⁰ atoms/cm³.

16. The display device according to claim 13,

wherein the first insulating film comprises an inorganic insulating film, and

wherein the second insulating film comprises an organic resin film.

17. The display device according to claim 13,

wherein the first metal oxide film and the second metal oxide film each comprise a region where an In content accounts for 40% or higher and 50% or lower of a total sum of In, M, and Zn atoms and a region where an M content accounts for 5% or higher and 30% or lower of the total sum of In, M, and Zn atoms, and

wherein the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

18. The display device according to claim 13,

wherein an atomic ratio of In to M and Zn is 4:

x;

y in the first metal oxide film and the second metal oxide film, where x is greater than or equal to 1.5 and less than or equal to 2.5 and y is greater than or equal to 2 and less than or equal to 4, and

wherein the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

19. The display device according to claim 13,

wherein an atomic ratio of In to M and Zn is 5:

x;

y in the first metal oxide film and the second metal oxide film, where x is greater than or equal to 0.5 and less than or equal to 1.5 and y is greater than or equal to 5 and less than or equal to 7, and

wherein the element M is one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

20. The display device according to claim 13,

wherein the first transistor has a dual-gate structure, and

wherein the second transistor has a single-gate structure.

21. An electronic device comprising:

the display device according to claim 13; and

a receiver.

22. The display device according to claim 13,

wherein the plurality of the first regions each have a size of greater than or equal to 0.5 nm and less than or equal to 3 nm, and

wherein the plurality of the second regions each have a size of greater than or equal to 0.5 nm and less than or equal to 3 nm.