Semiconductor device

• US 10,276,666 B2
• Filed: 08/30/2017
• Issued: 04/30/2019
• Est. Priority Date: 09/16/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Hoshi, Yasuyuki, Otsuki, Masahito, Yamada, Shoji, Shiigi, Takashi
• Primary Examiner(s): Coleman, William
• Application Number:
  US15/691,223
• Publication Number:
  US 20170365665A1
• Time in Patent Office: 608 Days
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

On a front surface of an n⁺-type SiC substrate becoming a drain region, an n⁻-type drift layer, a p-type base layer, and an n⁺-type source layer are sequentially formed by epitaxial growth. In the n⁺-type source layer, the p⁺-type contact region is selectively provided. A trench is provided penetrating the n⁺-type source layer and the p-type base layer in the depth direction and reaching the n⁻-type drift layer. In the trench, a gate electrode is provided via a gate insulating film. A width between adjacent trenches is, for example, 1 μm or less. A depth of the trench is, for example, 1 μm or less. The width is narrow whereby substantially the entire p-type base layer forms a channel. A cell includes a FinFET structure in which one channel is sandwiched between MOS gates on both side. Thus, ON resistance may be reduced and decreased reliability may be prevented.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type and including a wide bandgap semiconductor material having a bandgap wider than that of silicon;

a first semiconductor layer of the first conductivity type provided on a front surface of the semiconductor substrate, the first semiconductor layer including the wide bandgap semiconductor material and having an impurity concentration lower than that of the semiconductor substrate, the first semiconductor layer having a first side and a second side;

a second semiconductor layer of a second conductivity type provided on the first side of the first semiconductor layer opposite to the second side facing the semiconductor substrate, the second semiconductor layer including the wide bandgap semiconductor material and having a first side and a second side;

a third semiconductor layer of the first conductivity type provided on the first side of the second semiconductor layer opposite to the second side facing the semiconductor substrate, the third semiconductor layer including the wide bandgap semiconductor material and having a first side facing the second semiconductor layer, the second semiconductor layer substantially covering an entire area of the first side of the third semiconductor layer;

a second-conductivity-type semiconductor region provided selectively in the third semiconductor layer, penetrating the third semiconductor layer in a depth direction and reaching the second semiconductor layer such that a bottom surface of the second-conductivity-type semiconductor region contacts a surface of the first side of the second semiconductor layer, the second-conductivity-type semiconductor region having an impurity concentration higher than that of the second semiconductor layer;

a trench penetrating the third semiconductor layer and the second semiconductor layer and reaching the first semiconductor layer;

a gate insulating film provided on walls of the trench;

a gate electrode provided in the trench and sandwiched, in the trench, by the gate insulating film;

a first electrode provided in contact with the third semiconductor layer and the second-conductivity-type semiconductor region; and

a second electrode provided in contact with a rear surface of the semiconductor substrate, wherein

a width between the trench and an adjacent trench is 1 μ

m or less, and a depth of the trench is 1 μ

m or less, and

the semiconductor device has a breakdown voltage class of 1200V or higher.

2. The semiconductor device according to claim 1, wherein

the trench is arranged in planar layout having a striped shape parallel to the front surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein

the trench is arranged in a planar layout having a lattice shape parallel to the front surface of the semiconductor substrate.

4. The semiconductor device according to claim 1, comprising

a groove provided at a predetermined depth from surfaces on respective first sides of the third semiconductor layer and the second-conductivity-type semiconductor region, the respective first sides being opposite respective second sides of the third semiconductor layer and the second-conductivity-type semiconductor region facing the semiconductor substrate,

wherein the first electrode is provided to be in contact with the third semiconductor layer and the second-conductivity-type semiconductor region at an inner wall of the groove.

5. The semiconductor device according to claim 1, wherein

silicon carbide is used as the wide bandgap semiconductor material.

6. The semiconductor device according to claim 1, wherein the semiconductor substrate is a nitrogen-doped silicon carbide semiconductor substrate.

7. The semiconductor device according to claim 1, wherein the trench includes a first trench and a second trench spaced apart from each other and separated from each other by the second semiconductor layer and the third semiconductor layer, and

the third semiconductor layer extends contiguously between the first trench and the second trench.

8. The semiconductor device according to claim 1, wherein the trench includes a first trench and a second trench spaced apart from each other and separated from each other by the second semiconductor layer and the third semiconductor layer, and

a portion of the first semiconductor layer extends contiguously between the first trench and the second trench.