Semiconductor device and fabrication method thereof

• US 10,276,678 B2
• Filed: 09/01/2017
• Issued: 04/30/2019
• Est. Priority Date: 04/29/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsao, Chun-Han, Chen, Chih-Ming, Chen, Han-Yu, Wang, Szu-Yu, Chao, Lan-Lin, Tsai, Cheng-Yuan
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US15/693,849
• Publication Number:
  US 20170365514A1
• Time in Patent Office: 606 Days
• Field of Search: 257384
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/02068 during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor structure, a dielectric layer, a metal-semiconductor compound film and a cover layer. The semiconductor structure has an upper surface and a lateral surface. The dielectric layer encloses the lateral surface of the semiconductor structure and exposes the upper surface of the semiconductor structure. The metal-semiconductor compound film is on the semiconductor structure, wherein the dielectric layer exposes a portion of a surface of the metal-semiconductor compound film. The cover layer encloses the portion of the surface of the metal-semiconductor compound film exposed by the dielectric layer, and exposes the dielectric layer.

Claims

1. A method for fabricating semiconductor device, comprising:

receiving a substrate having a semiconductor structure formed thereon;

forming a metal layer over the substrate and the semiconductor structure;

thermally treating the metal layer to react the metal layer with the semiconductor structure to form a metal-semiconductor compound film on the semiconductor structure;

performing a first process to remove unreacted metal of the metal layer;

after performing the first process, forming a cover layer covering the metal-semiconductor compound film and exposing the substrate, wherein the cover layer encloses unreacted metal residues; and

after forming the cover layer, performing a wet cleaning operation to remove the unreacted metal residues enclosed by the cover layer.

2. The method of claim 1, wherein a material of the metal layer comprises nickel, platinum or a combination thereof, and a material of the semiconductor structure comprises silicon.

3. The method of claim 1, wherein forming the cover layer on the metal-semiconductor compound film comprises introducing an oxygen-containing gas reacting with the metal-semiconductor compound film to form an oxide cover layer.

4. The method of claim 1, wherein forming the cover layer on the metal-semiconductor compound film comprises introducing a nitrogen-containing gas reacting with the metal-semiconductor compound film to form a nitride cover layer.

5. The method of claim 1, wherein forming the cover layer on the metal-semiconductor compound film comprises introducing a carbon-containing gas reacting with the metal-semiconductor compound film to form a carbide cover layer.

6. The method of claim 1, wherein a cleaning solution of the wet cleaning operation comprises a sulfuric acid-hydrogen peroxide mixture (SPM) solution.

7. A method comprising:

providing a substrate having a gate electrode disposed over a semiconductor substrate;

forming a metal-semiconductor compound film on the gate electrode; and

introducing at least one of an oxygen-containing gas, a nitrogen-containing gas, or a carbon-containing gas to the metal-semiconductor compound film to form a cover layer over the metal-semiconductor compound film, wherein the at least one of the oxygen-containing gas, the nitrogen-containing gas, or the carbon-containing gas reacts with a metal residue on the substrate to form a covered metal residue; and

performing a cleaning process removing the covered metal residue after the forming the cover layer.

8. The method of claim 7, wherein the forming the metal-semiconductor compound film includes:

depositing a metal layer on a semiconductor material of the semiconductor substrate; and

thermally annealing the metal layer on the semiconductor material.

9. The method of claim 8, further comprising:

after the annealing, performing a first cleaning solution to remove a portion of an unreacted metal.

10. The method of claim 8, wherein the metal residue is a metal from the metal layer.

11. The method of claim 7, wherein the forming the metal-semiconductor compound film further includes forming the metal-semiconductor compound film on a source region and a drain region adjacent the gate electrode.

12. The method of claim 7, further comprising:

forming a conductive contact through an opening in the cover layer to interface the metal-semiconductor compound film.

13. The method of claim 7, wherein the forming the cover layer over the metal-semiconductor compound film is selectively forming the cover layer over the metal-semiconductor compound film.

14. The method of claim 7, wherein a first portion of the cover layer is formed over the gate electrode and a second portion of the cover layer is formed over a source region adjacent the gate electrode, wherein the first and second portions are not connected.

15. The method of claim 7, wherein the cleaning process is a wet clean.

16. A method for fabricating semiconductor device, comprising:

receiving a substrate having a semiconductor structure formed thereon;

forming a metal layer over the substrate and the semiconductor structure;

thermally treating the metal layer to form a metal-semiconductor compound film on the semiconductor structure including a first metal;

removing an unreacted portion of the metal layer;

after removing the unreacted portion, forming a cover layer of a dielectric of the first metal over the metal-semiconductor compound film;

performing a wet clean on a surface of the cover layer; and

forming an overlying layer on the cleaned surface of the cover layer.

17. The method of claim 16, wherein the wet clean is performed between about 85°

C. and 150°

C.

18. The method of claim 16, wherein the wet clean is performed using a sulfuric acid-hydrogen peroxide mixture (SPM) solution.

19. The method of claim 16, wherein the forming the overlying layer includes forming an interlayer dielectric (ILD).

20. The method of claim 19, further comprising:

forming a contact structure though the ILD and cover layer to the metal-semiconductor compound film.