Gate feature in FinFET device

• US 10,276,680 B2
• Filed: 07/18/2017
• Issued: 04/30/2019
• Est. Priority Date: 07/18/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Shen, Guan-Jie, Chang, Chia-Der, Lin, Chih-Hsiung
• Primary Examiner(s): Naraghi, Ali
• Application Number:
  US15/652,673
• Publication Number:
  US 20190027569A1
• Time in Patent Office: 651 Days
• Field of Search: None
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a fin structure, disposed on a substrate, that horizontally extends along a direction; and a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer, wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the direction to overlay at least a side portion of the fin structure that is located outside a vertical projection of a sidewall of the gate feature.

Claims

1. A semiconductor device, comprising:

a fin structure, disposed on a substrate, that horizontally extends along a direction; and

a gate feature that traverses the fin structure to overlay a central portion of the fin structure and further extends along the fin structure to overlay opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend away from respective sidewalls of the gate feature and away from the central portion of the fin structure.

2. The device of claim 1, wherein the gate feature comprises a gate dielectric layer and at least a metal gate layer.

3. The device of claim 1, wherein the gate dielectric layer comprises a high-k dielectric layer.

4. The device of claim 1, wherein the gate feature surrounds sidewalls and a top surface of the central portion of the fin structure.

5. The device of claim 1, wherein the gate feature surrounds sidewalls and a top surface of the at least side portion of the fin structure.

6. The device of claim 1, further comprising:

a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature.

7. The device of claim 1, further comprising:

an oxide layer disposed between the fin structure and the gate feature.

8. The device of claim 1, wherein the gate feature extends beyond the vertical projection of the sidewall of the gate feature by at least 2 nanometers.

9. A semiconductor device, comprising:

a fin structure, disposed on a substrate, that horizontally extends along a direction; and

a gate feature comprising a gate dielectric layer and at least a first metal gate layer overlaying the gate dielectric layer,

wherein the gate dielectric layer and the first metal gate layer traverse the fin structure to overlay a central portion of the fin structure and further extend along the fin structure to overlay opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend away from respective sidewalls of the gate feature and away from the central portion of the fin structure.

10. The device of claim 9, wherein the gate dielectric layer comprises a high-k dielectric layer.

11. The device of claim 9, wherein the gate feature comprises one or more metal gate layers, stacked on top to one another, on the first metal gate layer.

12. The device of claim 9, wherein the gate dielectric layer and the first metal gate layer surround sidewalls and a top surface of the central portion of the fin structure.

13. The device of claim 9, further comprising:

a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature.

14. The device of claim 9, further comprising:

an oxide layer disposed between the fin structure and the gate feature.

15. The device of claim 9, wherein the gate feature extends beyond the vertical projection of the sidewall of the gate feature by about 2 nanometers.

16. The device of claim 9, further comprising:

a dielectric layer, at a respective side of the gate feature, that overlays at least the side portion of the fin structure.

17. A semiconductor device, comprising:

a fin structure, disposed on a substrate, that horizontally extends along a direction;

a gate feature that traverses the fin structure to overlay a central portion of the fin structure and further extends along the fin structure to overlay opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend away from respective sidewalls of the gate feature and away from the central portion of the fin structure;

a pair of source/drain features, along the fin structure, that are disposed at respective sides of the gate feature; and

an oxide layer disposed between the fin structure and the gate feature.

18. The device of claim 17, wherein the gate feature comprises a gate dielectric layer and at least a metal gate layer.

19. The device of claim 17, wherein the gate dielectric layer comprises a high-k dielectric layer.