Formation of self-aligned bottom spacer for vertical transistors

• US 10,276,687 B1
• Filed: 12/20/2017
• Issued: 04/30/2019
• Est. Priority Date: 12/20/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bao, Ruqiang, Jagannathan, Hemanth, Lee, Choonghyun, Mochizuki, Shogo
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US15/848,861
• Time in Patent Office: 496 Days
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02175 characterised by the metal H01L21/02197 takes precedence
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/02332 into an oxide layer, e.g. changing SiO to SiON
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

A method of fabricating a semiconductor device includes forming a fin on a substrate. Source/drain regions are arranged on the substrate on opposing sides of the fin. The method includes depositing a semiconductor layer on the source/drain regions. The method includes depositing a germanium containing layer on the fin and the semiconductor layer. The method further includes applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a fin on a substrate;

forming source/drain regions arranged on the substrate on opposing sides of the fin;

depositing a semiconductor layer on the source/drain regions;

depositing a germanium containing layer on the fin and the semiconductor layer; and

applying an anneal operation configured to chemically react the semiconductor layer with the germanium containing layer and form a silicon oxide layer.

2. The method of claim 1, wherein the semiconductor layer comprises silicon germanium.

3. The method of claim 2, wherein, subsequent to annealing, the silicon oxide layer is arranged on a silicon germanium layer that includes a higher content of germanium than the semiconductor layer.

4. The method of claim 2, wherein the silicon germanium comprises from about 20 to about 60 atomic percentage (%) germanium.

5. The method of claim 3, wherein the silicon germanium layer that includes a higher content of germanium comprises from about 40 to about 80 atomic % germanium.

6. The method of claim 1, wherein the germanium containing layer comprises germanium oxide.

7. A method of forming a semiconductor device, the method comprising:

forming a fin on a substrate;

forming source/drain regions arranged on the substrate on opposing sides of the fin;

depositing a first silicon germanium layer on the source/drain regions;

depositing a germanium containing layer on the fin and the first silicon germanium layer;

annealing to chemically react the first silicon germanium layer with the germanium containing layer and form a silicon oxide layer arranged on a second silicon germanium layer with an increased germanium content than the first silicon germanium layer; and

performing a nitridation process to increase a nitrogen content of the silicon oxide layer and form a bottom spacer.

8. The method of claim 7, wherein the nitridation process comprises rapid thermal nitridation or plasma nitridation.

9. The method of claim 7, wherein the germanium containing layer comprises GeO₂.

10. The method of claim 7, wherein, subsequent to performing the nitridation process, the bottom spacer comprises SiON.

11. The method of claim 7, wherein, subsequent to performing the nitridation process, the germanium containing layer on sidewalls of the fin forms GeON.

12. The method of claim 11, further comprising removing the GeON and forming a metal gate on the bottom spacer.

13. A method of fabricating a semiconductor device, the method comprising:

depositing a first silicon germanium layer on a source/drain region arranged on a substrate,

depositing a germanium oxide layer on the fin and the first silicon germanium layer; and

chemically reacting the first silicon germanium layer with the germanium oxide layer to form a silicon oxide layer arranged on a second silicon germanium layer with an increased germanium content than the first silicon germanium layer.

14. The method of claim 13, wherein the second silicon germanium layer comprises from about 20 to about 30 atomic % more germanium than the first silicon germanium layer.

15. The method of claim 13 further comprising performing a nitridation process to increase a nitrogen content of the silicon oxide layer.

16. The method of claim 15, wherein the nitridation process is performed at a temperature of from about 600 to about 800°

C.

17. The method of claim 13, wherein the nitridation process forms a SiON layer on the second silicon germanium layer.

18. The method of claim 13, wherein the silicon oxide layer comprises substantially pure SiO₂.