Memory device and fabrication method thereof

• US 10,276,794 B1
• Filed: 10/31/2017
• Issued: 04/30/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Tai-Yen, Wei, Hui-Hsien, Wen, Wei-Chih, Dai, Pin-Ren, Lee, Chien-Min, Tsai, Han-Ting, Shieh, Jyu-Horng, Lin, Chung-Te
• Primary Examiner(s): Tran, Michael T
• Application Number:
  US15/799,416
• Publication Number:
  US 20190131524A1
• Time in Patent Office: 546 Days
• Field of Search: 365148, 365158
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 70/023 by chemical vapor deposition, e.g. MOCVD, ALD
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8416 adapted for supplying ionic species
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/884 based on at least one element of group IIIA, IVA or VA, e.g. elemental or compound semiconductors compounds of sulfur, selenium or tellurium, e.g. chalcogenides H10N70/882; oxides or nitrides H10N70/883

Abstract

A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

Claims

1. A memory device, comprising:

a substrate having a memory region and a logic region, wherein the substrate comprises a metallization pattern therein;

an etch stop layer over the substrate, wherein the etch stop layer has a first portion over the memory region and a second portion over the logic region;

a protective layer covering the first portion of the etch stop layer, wherein the protective layer does not cover the second portion of the etch stop layer; and

a resistance switching element over the memory region, wherein the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.

2. The memory device of claim 1, wherein the protective layer is an Al-based layer.

3. The memory device of claim 1, further comprising:

a bottom electrode via connecting the resistance switching element to the metallization pattern, wherein the bottom electrode via is in the protective layer and the first portion of the etch stop layer.

4. The memory device of claim 3, further comprising:

a dielectric layer over the protective layer, wherein the resistance switching element is over the dielectric layer, and the bottom electrode via is further in the dielectric layer.

5. The memory device of claim 4, wherein the dielectric layer has a first portion and a second portion thicker than the first portion, and the second portion of the dielectric layer surrounds the bottom electrode via.

6. The memory device of claim 4, wherein the dielectric layer is not in the logic region.

7. The memory device of claim 1, further comprising:

a first interlayer dielectric layer covering the resistance switching element; and

a second interlayer dielectric layer over the logic region, wherein the first interlayer dielectric layer and the second interlayer dielectric layer have an interface therebetween.

8. The memory device of claim 7, wherein a top surface of the first portion of the etch stop layer is in contact with the protective layer, and a top surface of the second portion of the etch stop layer is in contact with the second interlayer dielectric layer.

9. The memory device of claim 1, further comprising:

a circuit over the logic region, wherein the circuit is electrically connected to the metallization pattern through the second portion of the etch stop layer.

10. A memory device, comprising:

a substrate having a memory region and a logic region, wherein the substrate comprises a metallization pattern therein;

an etch stop layer over the substrate, wherein the etch stop layer has a first portion over the memory region and a second portion over the logic region;

a protective layer extending along a top surface of the first portion of the etch stop layer and terminating prior to reaching a top surface of the second portion of the etch stop layer; and

a resistance switching element over the memory region, wherein the resistance switching element is electrically connected to the metallization pattern through the first portion of the etch stop layer and the protective layer.

11. The memory device of claim 10, wherein the protective layer is an Al-based layer.

12. The memory device of claim 10, further comprising:

a first interlayer dielectric layer over the logic region; and

a dielectric layer between the resistance switching element and the protective layer, wherein the dielectric layer and the first interlayer dielectric layer have an interface therebetween.

13. The memory device of claim 10, further comprising:

a first interlayer dielectric layer over the logic region; and

a circuit over the first interlayer dielectric layer, wherein the circuit is electrically connected to the metallization pattern through the second portion of the etch stop layer.

14. The memory device of claim 13, further comprising:

a second interlayer dielectric layer over the memory region, wherein the first and second interlayer dielectric layers have an interface therebetween.

15. The memory device of claim 13, wherein a top surface of the first portion of the etch stop layer is in contact with the protective layer, and a top surface of the second portion of the etch stop layer is in contact with the first interlayer dielectric layer.

16. A method for fabricating a memory device, comprising:

forming an etch stop layer over a substrate;

forming a protective layer over the etch stop layer, wherein the protective layer has a first portion over a memory region of the substrate and a second portion over a logic region of the substrate;

forming a resistance switching element over the first portion of the protective layer;

forming an interlayer dielectric layer over the resistance switching element and the first and second portions of the protective layer; and

etching the interlayer dielectric layer to expose the second portion of the protective layer.

17. The method of claim 16, wherein the protective layer has a higher etch resistance to the etching the interlayer dielectric layer than that of the interlayer dielectric layer.

18. The method of claim 16, wherein the protective layer has a higher etch resistance to the etching the interlayer dielectric layer than that of the etch stop layer.

19. The method of claim 16, further comprising:

removing the second portion of the protective layer while leaving the first portion of the protective layer.

20. The method of claim 19, wherein the removing the second portion of the protective layer is performed by an etching process, and the etch stop layer has a higher etch resistance to the etching process than that of the protective layer.