Half bridge power conversion circuits using GaN devices

• US 10,277,048 B2
• Filed: 12/11/2017
• Issued: 04/30/2019
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Toole, Colleen O
• Application Number:
  US15/838,026
• Publication Number:
  US 20180102661A1
• Time in Patent Office: 505 Days
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02J 7/00 Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
• CPC Class Codes: H02M 1/0048 : Circuits or arrangements for reducing losses using snubbers H02M1/34
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H02M 3/155 : using semiconductor devices only
• CPC Class Codes: H02M 3/157 : with digital control
• CPC Class Codes: H02M 3/1584 : with a plurality of power processing stages connected in parallel
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/102 : in field-effect transistor switches
• CPC Class Codes: H03K 19/018507 : Interface arrangements
• CPC Class Codes: H03K 3/012 : Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356017 : using additional transistors in the input circuit H03K3/356104, H03K3/3562 take precedence
• CPC Class Codes: Y02B 40/00 : Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Claims

1. A half-bridge circuit comprising:

a low side circuit disposed on a first semiconductor die, and including a GaN-based low side switch and a GaN-based level shift circuit; and

a high side circuit disposed on a second semiconductor die, and including a GaN-based high side switch that is coupled to and controlled by the GaN-based level shift circuit.

2. The half-bridge circuit of claim 1 wherein the GaN-based level shift circuit receives an input signal at a first voltage and generates an output signal at a second voltage, wherein the second voltage is higher than the first voltage and the second voltage controls the GaN-based high side switch.

3. The half-bridge circuit of claim 2 wherein the second voltage is at least 20 volts greater than the first voltage.

4. The half-bridge circuit of claim 1 wherein the GaN-based level shift circuit includes an enhancement mode GaN transistor.

5. The half-bridge circuit of claim 1 wherein the high side circuit includes a level shift receiver circuit that receives a control signal from the GaN-based level shift circuit and in response controls a high side switch driver circuit that operates the GaN-based high side switch.

6. A half-bridge circuit comprising:

a high side GaN-based switch coupled between a voltage source and a switch-node;

a low side GaN-based switch coupled between the switch-node and a ground; and

a GaN-based level shift circuit coupled to the high side GaN-based switch and configured to receive an input signal, level shift the input signal from a first voltage to a second voltage and transmit an output signal at the second voltage to a circuit that controls the high side GaN-based switch,

wherein the high side GaN-based switch is disposed on a first monolithic die and the low side GaN-based switch is disposed on a second monolithic die, and

wherein the GaN-based level shift circuit is disposed on the second monolithic die and is configured to transmit the output signal from the second monolithic die to the first monolithic die.

7. The half-bridge circuit of claim 6 wherein the first monolithic die includes a receiver circuit that receives the output signal and in response controls a high side switch driver circuit that operates the high side GaN-based switch.

8. The half-bridge circuit of claim 6 wherein the second voltage is higher than the first voltage.

9. The half-bridge circuit of claim 8 wherein the second voltage is at least 20 volts higher than the first voltage.

10. The half-bridge circuit of claim 6 wherein the GaN-based level shift circuit includes an enhancement mode GaN transistor.

11. A power conversion circuit comprising:

a first semiconductor device including a first GaN-based switch coupled between a voltage source and a switch-node; and

a second semiconductor device including a second GaN-based switch coupled between the switch-node and a ground, and further including a GaN-based level shift circuit coupled to and configured to control the first GaN-based switch,

wherein the first semiconductor device is disposed on a first die and the second semiconductor device is disposed on a second die.

12. The power conversion circuit of claim 11 wherein the level shift circuit is configured to send a level shift signal from the second semiconductor device to the first semiconductor device.

13. The power conversion circuit of claim 12 wherein the first semiconductor device includes a receiver circuit that receives the level shift signal and in response sends a control signal to a first driver circuit that controls the first GaN-based switch.

14. The power conversion circuit of claim 12 wherein the level shift circuit receives a signal at a first voltage and in response sends the level shift signal to the first semiconductor device at a second voltage.

15. The power conversion circuit of claim 14 wherein the second voltage is higher than the first voltage.

16. The power conversion circuit of claim 14 wherein the second voltage is at least 20 volts higher than the first voltage.

17. The power conversion circuit of claim 11 wherein the level shift circuit includes an enhancement mode GaN transistor.

18. The power conversion circuit of claim 11 wherein the level shift circuit includes an inverter having a resistor pull up and a pull down transistor.