Transmitter and shortening method thereof

• US 10,277,251 B2
• Filed: 04/15/2016
• Issued: 04/30/2019
• Est. Priority Date: 03/02/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kyung-Joong, Myung, Se-ho, Jeong, Hong-sil
• Primary Examiner(s): Torres, Joseph D
• Application Number:
  US15/130,181
• Publication Number:
  US 20160261374A1
• Time in Patent Office: 1,110 Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: H03M 13/1148 Structural properties of the code parity-check or generator matrix
• CPC Class Codes: H03M 13/1157 Low-density generator matrices [LDGM]
• CPC Class Codes: H03M 13/1165 QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
• CPC Class Codes: H03M 13/1191 Codes on graphs other than LDPC codes
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/253 with concatenated codes
• CPC Class Codes: H03M 13/255 with Low Density Parity Check [LDPC] codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/611 Specific encoding aspects, e.g. encoding by means of decoding
• CPC Class Codes: H03M 13/618 Shortening and extension of codes
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0063 Single parity check
• CPC Class Codes: H04L 1/0069 Puncturing patterns

Abstract

A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to constitute Low Density Parity Check (LDPC) information bits including the outer-encoded bits and zero bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the LDPC information bits are divided into a plurality of bit groups, and wherein the zero padder pads zero bits to at least some of the plurality of bit groups, each of which is formed of a same number of bits, to constitute the LDPC information bits based on a predetermined shortening pattern which provides that the some of the plurality of bit groups are not sequentially disposed in the LDPC information bits.

Claims

1. A television (TV) broadcasting signal transmitting apparatus for transmitting layer1-detail (L1D) signaling information for TV broadcasting, the TV broadcasting transmitting apparatus being operable in a mode among a plurality of modes, the TV broadcasting transmitting apparatus comprising:

a zero padder configured to receive L1D input bits to be encoded and modulated, fill a bit space of a predetermined size with the L1D input bits and one or more zero padding bits based on a zero padding order of the mode, if a size of the L1D input bits is less than the predetermined size, wherein the L1D input bits are based on the L1D signaling information;

an encoder configured to encode bits included in the bit space based on a low density parity check (LDPC) code having a code rate of the mode being 3/15 and a code length of the mode being 16200 bits;

a zero remover configured to remove the one or more zero padding bits from among the encoded bits included in the bit space;

a mapper configured to modulate bits, included in the bit space remaining after the removing, to constellation points based on a quadrature phase shift keying (QPSK) modulation of the mode;

a signal generator configured to generate a TV broadcasting signal based on the constellation points using orthogonal frequency division (OFDM) processing; and

a transmitter configured to transmit the TV broadcasting signal,

wherein the zero padder is configured to fill the bit space of the predetermined size by dividing the bit space into a plurality of bit group areas, calculating a number of zero padding bits to be padded, determining at least one bit group area to which the one or more zero padding bits are padded among the plurality of bit group areas based on the calculated number and the zero padding order of the mode and padding the one or more zero padding bits to the at least one bit group area, and

wherein the zero padding order of the mode is represented below;

2. The apparatus of claim 1, wherein the zero padder is further configured to calculate a number of the at least one bit group area based on a following equation:

3. The apparatus of claim 2, wherein the zero padder is further configured to pad the one or more zero padding bits to all bits of a π

_s(0)-th bit group area, a π

_s(1)-th bit group area, . . . , a π

_s(N_pad−

1)-th bit group area among the plurality of bit group areas based on the zero padding order of the mode.

4. The apparatus of claim 3, wherein the zero padder is further configured to additionally pad the one or more zero padding bits to K_ldpc−

N_outer−

360×

N_pad zero padding bits from a first bit of a π

_s(N_pad)-th bit group area based on the zero padding order of the mode.