Phase rotation circuit for eye scope measurements

• US 10,277,431 B2
• Filed: 05/23/2017
• Issued: 04/30/2019
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Malek, Leila
• Application Number:
  US15/603,404
• Publication Number:
  US 20180083638A1
• Time in Patent Office: 707 Days
• Field of Search: 375354
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H04L 2203/02 differential
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

Claims

1. A method comprising:

forming a received data signal using a multi-input comparator detecting a respective sub-channel of a plurality of mutually orthogonal sub-channels carried by a multi-wire bus;

generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock having an applied sub-channel specific delay associated with the respective sub-channel of the plurality of mutually orthogonal sub-channels;

generating, using a data slicer and the data sampling clock, a receive sample of the received data signal; and

generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

2. The method of claim 1, further comprising adjusting a data slicer threshold of the data slicer to obtain the receive sample using a first decision feedback equalization (DFE)-compensated slicer that includes a DFE offset voltage.

3. The method of claim 2, further comprising simultaneously obtaining a data-sampling phase error measurement using a second DFE-compensated slicer having a second DFE offset voltage.

4. The method of claim 3, wherein the first and second DFE-compensated slicers utilize slicing thresholds that are offset with a positive DFE offset and a negative DFE offset, respectively.

5. The method of claim 1, further comprising generating the receive sample using an integrate and hold circuit.

6. The method of claim 1, wherein the data slicer generates a data sample and a data phase error signal.

7. The method of claim 6, further comprising processing the data phase error signal using a charge pump circuit to generate a local oscillator control signal for the local oscillator.

8. The method of claim 1, wherein one of the data-sampling clock and the variable-phase-offset eye-measurement clock is generated by the local oscillator, and wherein the other of the data-sampling clock and the variable-phase-offset eye-measurement clock is generated using the phase interpolator.

9. The method of claim 1, further comprising determining a phase interpolator delay value associated with the phase interpolator by:

selecting an output of the phase interpolator as the variable-phase-offset eye-measurement clock and obtaining a first phase interpolator code that aligns the output of the phase interpolator to an edge of an eye;

selecting an output of the local oscillator as the variable-phase-offset eye-measurement clock and obtaining a second phase interpolator code that aligns the output of the local oscillator to an edge of an eye; and

comparing the first and second phase interpolator codes to determine the phase interpolator delay value.

10. The method of claim 9, wherein the variable-phase-offset eye-measurement clock and the data sampling clock are each selected via respective multiplexers receiving outputs of the phase interpolator and the local oscillator.

11. An apparatus comprising:

at least one multi-input comparator (MIC) connected to a plurality of wires of a multi-wire bus, the MIC configured to form a received data signal corresponding to a detected sub-channel of a plurality of mutually orthogonal sub-channels carried on the plurality of wires of the multi-wire bus;

a local oscillator and an adjustable phase interpolator configured to generate a data-sampling clock and a variable-phase-offset eye-measurement clock having an applied sub-channel specific delay associated with the respective sub-channel of the plurality of mutually orthogonal sub-channels;

at least one data slicer configured to receive the data sampling clock, and configured to generate a receive sample of the received data signal; and

at least one eye slicer configured to receive the variable-phase-offset eye-measurement clock, and configured to generate a plurality of eye characteristic measurements.

12. The apparatus of claim 11, wherein the at least one eye slicer comprises a first eye slicer having a positive threshold offset, and a second eye slicer having a negative threshold offset.

13. The apparatus of claim 11, further comprising first decision feedback equalization (DFE)-compensated slicer that includes a DFE offset voltage configured to adjust the data slicer threshold to obtain the receive sample.

14. The apparatus of claim 13, further comprising a second DFE-compensated slicer having a second DFE offset voltage configured to simultaneously obtain a data-sampling phase error measurement.

15. The apparatus of claim 14, wherein the first and second DFE-compensated slicers utilize slicing thresholds that are offset with a positive DFE offset and a negative DFE offset, respectively.

16. The apparatus of claim 11, further comprising an integrate and hold circuit configured to generate the receive sample.

17. The apparatus of claim 11, wherein the data slicer is configured to generate a data sample and a data phase error signal.

18. The apparatus of claim 17, further comprising a charge pump circuit configured to process the data phase error signal to generate a local oscillator control signal for the local oscillator.

19. The apparatus of claim 11, further comprising a tunable delay element configured to apply the sub-channel specific delay to the data sampling clock and the variable-phase-offset eye-measurement clock.

20. The apparatus of claim 11, wherein the phase interpolator is configured via a phase interpolator code, the phase interpolator code used in determining a phase interpolator delay value associated with the phase interpolator by:

selecting, via a plurality of multiplexers, an output of the phase interpolator as the variable-phase-offset eye-measurement clock and obtaining a first phase interpolator code that aligns the output of the phase interpolator to an edge of an eye;

selecting, via the plurality of multiplexers, an output of the local oscillator as the variable-phase-offset eye-measurement clock and obtaining a second phase interpolator code that aligns the output of the local oscillator to an edge of an eye; and

comparing the first and second phase interpolator codes to determine the phase interpolator delay value.