Method for encoding real number M-ary signal and encoding apparatus using same

• US 10,277,434 B2
• Filed: 04/21/2015
• Issued: 04/30/2019
• Est. Priority Date: 03/27/2015
• Status: Active Grant

• Current Assignee: InterDigital Patent Holdings, Inc. (InterDigital, Inc.)
• Original Assignee: IDAC Holdings, Inc. (InterDigital, Inc.)
• Inventors: Chung, Hae, Chung, Han
• Primary Examiner(s): Lee, Siu M
• Application Number:
  US15/561,904
• Publication Number:
  US 20180123839A1
• Time in Patent Office: 1,470 Days
• CPC Class Codes: H03M 5/02 Conversion to or from representation by pulses
• CPC Class Codes: H03M 5/20 the pulses having more than three levels
• CPC Class Codes: H03M 7/30 Compression speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/365 Modulation using digital generation of the modulated carrier (not including modulation of a digitally generated carrier)
• CPC Class Codes: H04L 27/366 Arrangements for compensating undesirable properties of the transmission path between the modulator and the demodulator

Abstract

Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N₁ number of M₁-ary signals, a second signal generator which receives the second input code and generates N₂ number of M₂-ary signals, and a first time division multiplexing module which temporally multiplexes the N₁ number of M₁-ary signals and the N₂ number of M₂-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A₂/A₁) used for M₁-ary and M₂-ary signals to minimize a transmission error rate.

Claims

1. An M-ary encoding apparatus, comprising:

a coding unit configured to code, from binary data, to generate a first coded sequence and a second coded sequence, the coding unit including a serial-parallel converter configured to convert serial binary data to K-bit parallel data and a symbol mapper configured to map the K-bit parallel data to the first coded sequence and the second coded sequence;

a signal generator configured to generate;

(1) from the first coded sequence, a first number of M₁-ary signals; and

(2) from the second coded sequence, a second number of M₂-ary signals; and

a multiplexer configured to multiplex the first number of M₁-ary signals and the second number of M₂-ary signals to generate a multiplexed M-ary signal, where M₁ and M₂ are integers.

2. The M-ary encoding apparatus of claim 1, wherein the coding unit is configured to code:

(1) a first set of K binary data bits to generate a first portion of the first coded sequence and the second coded sequence; and

(2) one or more further sets of K binary data bits to generate one or more further portions of the first coded sequence and the second coded sequence.

3. The M-ary encoding apparatus of claim 1, wherein the multiplexer is configured to time and/or frequency multiplex the first number of M₁-ary signals and the second number of M₂-ary signals.

4. The M-ary encoding apparatus of claim 1, wherein the first number of M₁-ary signals are N₁ number of M₁-ary signals and the second number of M₂-ary signals are N₂ number of M₂-ary signals, where N₁ and N₂ are integers.

5. The M-ary encoding apparatus of claim 1, further comprising:

a processor configured to;

determine, as a determined result, any of;

(1) an error rate of a channel;

(2) a noise level associated with the channel;

or (3) a signal to noise ratio (SNR) per bit;

establish a real number M based on the determined result; and

determine M₁, as M₁=[M], and M₂, as M₂=[M]+1, where [M] is a greatest integer which is not greater than the real number M.

6. The M-ary encoding apparatus of claim 2, wherein:

the first number of M₁-ary signals are N₁ number of M₁-ary signals and the second number of M₂-ary signals are N₂ number of M₂-ary signals, where N₁ and N₂ are integers; and

K is determined using an equation K=[N₁ log 2 M₁+N₂ log 2 M₂].

7. The M-ary encoding apparatus of claim 4, wherein:

N=N₁+N₂;

N_j (j=1 or

     2) is determined based on a transmission efficiency level and a calculation complexity level;

the transmission efficiency level includes a mean transmission bit number per signal component of the multiplexed M-ary signal; and

the mean transmission bit number per signal component is calculated as [N₁ log 2 M₁+N₂ log 2 M₂]/N.

8. The M-ary encoding apparatus of claim 7, wherein

N_j (j=1 or 2) is 1 on a condition that M_j (j=1 or 2) is 2, 4, 8, 16, or 32,

N_j (j=1 or 2) is 2 on a condition that M_j (j=1 or 2) is 3, 6, 12, or 23,

N_j (j=1 or 2) is 3 on a condition that M_j (j=1 or 2) is 21 or 26,

N_j (j=1 or 2) is 4 on a condition that M_j (j=1 or 2) is 5, 10, 20, or 27,

N_j (j=1 or 2) is 5 on a condition that M_j (j=1 or 2) is 7, 11, 13, 14, 19, 22, 25, or 28,

N_j (j=1 or 2) is 6 on a condition that M_j (j=1 or 2) is 9, 15, 18, or 29,

N_j (j=1 or 2) is 7 on a condition that M_j (j=1 or 2) is 24,

N_j (j=1 or 2) is 8 on a condition that M_j (j=1 or 2) is 30,

N_j (j=1 or 2) is 10 on a condition that M_j (j=1 or 2) is 31, and

N_j (j=1 or 2) is 12 on a condition that M_j (j=1 or 2) is 17.

9. The M-ary encoding apparatus of claim 1, wherein:

the signal generator includes;

a first pulse amplitude modulation (PAM) generator configured to generate the first number of first PAM signals, the first PAM signals having M₁ number of voltage levels, and

a second PAM generator configured to generate the second number of second PAM signals, the second PAM signals having M₂ number of voltage levels; and

the multiplexer includes a first multiplexing device configured to temporally multiplex the first PAM signals and the second PAM signals.

10. The M-ary encoding apparatus of claim 9, wherein:

the signal generator further includes;

a third PAM generator configured to generate the first number of third PAM signals, the third PAM signals having M₁ number of voltage levels, and

a fourth PAM generator configured to generate the second number of fourth PAM signals, the fourth PAM signals having M₂ number of voltage levels; and

the multiplexer further includes a second multiplexing device configured to temporally multiplex the third PAM signals and the fourth PAM signals.

11. The M-ary encoding apparatus of claim 10, wherein:

the first multiplexing device is configured to temporally multiplex the first PAM signals and the second PAM signals such that the first PAM signals are first in time and the second PAM signals are second in time, as a first PAM multiplexed signal; and

the second multiplexing device is configured to multiplex the third PAM signals and the fourth PAM signals such that the third PAM signals are first in time and the fourth PAM signals are second in time, as a second PAM multiplexed signal.

12. The M-ary encoding apparatus of claim 11, further comprising:

a first multiplier configured to multiply the first PAM multiplexed signal by a cosine signal to generate an I channel modulation signal;

a second multiplier configured to multiply the second PAM multiplexed signal by a sine signal, which is orthogonal to the cosine signal, to generate a Q channel modulation signal; and

an adder configured to sum the I channel modulation signal and the Q channel modulation signal.

13. The M-ary encoding apparatus of claim 1, further comprising:

a K-frequency divider configured to divide an input clock signal by K to generate a divided clock signal; and

an N-frequency multiplier configured to multiply a frequency of the divided clock signal by N to generate a multiplied clock signal, wherein;

the symbol mapper is configured to operate in response to the divided clock signal, and

the signal generator is configured to operate in response to the multiplied clock signal.

14. The M-ary encoding apparatus of claim 1, wherein the multiplexed M-ary signal is one of:

(1) a N time-dimensional M-ary PAM signal;

(2) a N time-dimensional M-ary amplitude shift keying (ASK) signal;

(3) a N time-dimensional M-ary frequency shift keying (FSK) signal;

(4) a N time-dimensional Mary phase shift keying (PSK) signal;

(5) a N time-dimensional M-ary quadrature amplitude modulation (QAM) signal;

or (6) a N time-dimensional and L frequency dimensional M-ary amplitude, phase, and frequency modulation (APFSK) signal.

15. The M-ary encoding apparatus of claim 14, further comprising a processor configured to allocate one or more codes for a channel environment having inter-channel interference (ICI) above a threshold such that frequencies are skipped when generating the N time-dimensional and L frequency-dimensional M-ary APFSK signal.

16. An M-ary encoding method, the method comprising:

coding, from binary data, to generate a first coded sequence and a second coded sequence by converting serial binary data to K-bit parallel data and mapping, by a symbol mapper, the K-bit parallel data to the first coded sequence and the second coded sequence;

generating;

(1) from the first coded sequence, a first number of M₁-ary signals; and

(2) from the second coded sequence, a second number of M₂-ary signals; and

multiplexing the first number of M₁-ary signals and the second number of M₂-ary signals to generate a multiplexed M-ary signal, where M₁ and M₂ are integers.

17. The M-ary encoding method of claim 16, wherein the coding of the first coded sequence and the second coded sequence includes coding (1) a first set of K binary data bits to generate a first portion of the first coded sequence and the second coded sequence;

and (2) one or more further sets of K binary data bits to generate one or more further portions of the first coded sequence and the second coded sequence.

18. The M-ary encoding method of claim 16, wherein the multiplexing of the first number of M₁-ary signals and the second number of M₂-ary signals includes time and/or frequency multiplexing the first number of M₁-ary signals and the second number of M₂-ary signals.

19. The M-ary encoding method of claim 16, wherein the first number of M₁-ary signals are N₁ number of M₁-ary signals and the second number of M₂-ary signals are N₂ number of M₂-ary signals, where N₁ and N₂ are integers.

20. The M-ary encoding method of claim 16, further comprising:

determining, as a determined result, any of;

(1) an error rate of a channel;

(2) a noise level associated with the channel;

or (3) a signal to noise ratio (SNR) per bit;

establishing a real number M based on the determined result; and

determining M₁, as M₁=[M], and M₂, as M₂=[M]+1, where [M] is a greatest integer which is not greater than the real number M.

21. The M-ary encoding method of claim 17, wherein the first number of M₁-ary signals are N₁ number of M₁-ary signals and the second number of M₂-ary signals are N₂ number of M₂-ary signals, where N₁ and N₂ are integers, the method further comprising

determining K using an equation K=[N₁ log 2 M₁+N₂ log 2 M₂].

22. The M-ary encoding method of claim 19, further comprising selecting N₁ and N₂ based on M₁ and M₂.

23. The M-ary encoding method of claim 18, wherein:

the generating of the first number of M₁-ary signals includes generating N₁ number of first PAM signals, the first PAM signals having M₁ number of voltage levels;

the generating of the second number of M₂-ary signals includes generating N₂ number of second PAM signals, the second PAM signals having M₂ number of voltage levels;

the generating of the first number of M₁-ary signals further includes generating N₁ number of third PAM signals, the third PAM signals having M₁ number of voltage levels;

the generating of the second number of M₂-ary signals further includes generating N₂ number of fourth PAM signals, the fourth PAM signals having M₂ number of voltage levels; and

the multiplexing of the first number of M₁-ary signals and the second number of M₂-ary signals includes temporally multiplexing (1) the first PAM signals and the second PAM signals, and (2) the third PAM signals and the fourth PAM signals.

24. The M-ary encoding method of claim 23, wherein the temporally multiplexing of the first PAM signals and the second PAM signals includes:

(1) temporally multiplexing the first PAM signals and the second PAM signals such that the first PAM signals are first in time and the second PAM signals are second in time, as a first PAM multiplexed signal; and

(2) temporally multiplexing the third PAM signals and the fourth PAM signals such that the third PAM signals are first in time and the fourth PAM signals are second in time, as a second PAM multiplexed signal.

25. The M-ary encoding method of claim 24, further comprising:

multiplying the first PAM multiplexed signal by a cosine signal to generate an I channel modulation signal;

multiplying the second PAM multiplexed signal by a sine signal, which is orthogonal to the cosine signal, to generate a Q channel modulation signal; and

summing the I channel modulation signal and the Q channel modulation signal.

26. The M-ary encoding method of claim 18, wherein the multiplexed M-ary signal is one of:

(1) a N time-dimensional M-ary PAM signal;

(2) a N time-dimensional M-ary amplitude shift keying (ASK) signal;

(3) a N time-dimensional M-ary frequency shift keying (FSK) signal;

(4) a N time-dimensional Mary phase shift keying (PSK) signal;

(5) a N time-dimensional M-ary quadrature amplitude modulation (QAM) signal;

or (6) a N time-dimensional and L frequency dimensional M-ary amplitude, phase, and frequency modulation (APFSK) signal.

27. A real number M-ary encoding apparatus comprising:

a coding unit for coding binary bit units of K bit length binary data to generate a first input code and a second input code, wherein K is an integer, the coding unit comprising a serial-parallel converter configured to convert serial binary data to parallel binary bit units of the K bit length binary data and a symbol mapper configured to map the parallel binary bit units to the first input code and the second input code;

a first signal generator for receiving the first input code and generating N₁ number of M₁-ary signals;

a second signal generator for receiving the second input code and generating N₂ number of M₂-ary signals; and

a time division multiplexer for temporally multiplexing the N₁ number of M₁-ary signals and the N₂ number of M₂-ary signals to generate a real number M-ary signal, wherein N₁, N₂, M₁, and M₂ are integers, respectively.

28. A real number M-ary encoding method comprising:

coding binary bit units of K bit length binary data, wherein K is an integer by converting serial binary data to parallel binary bit units of the K length binary data;

mapping, by a symbol mapper, the parallel binary bit units to N₁ number of M₁-ary signals and N₂ number of M₂-ary signals; and

temporally multiplexing the N₁ number of M₁-ary signals and N₂ number of M₂-ary signals to generate a first real number M-ary signal, wherein N₁, N₂, M₁, and M₂ are integers, respectively.