Method for encoding real number M-ary signal and encoding apparatus using same
First Claim
1. An M-ary encoding apparatus, comprising:
- a coding unit configured to code, from binary data, to generate a first coded sequence and a second coded sequence, the coding unit including a serial-parallel converter configured to convert serial binary data to K-bit parallel data and a symbol mapper configured to map the K-bit parallel data to the first coded sequence and the second coded sequence;
a signal generator configured to generate;
(1) from the first coded sequence, a first number of M1-ary signals; and
(2) from the second coded sequence, a second number of M2-ary signals; and
a multiplexer configured to multiplex the first number of M1-ary signals and the second number of M2-ary signals to generate a multiplexed M-ary signal, where M1 and M2 are integers.
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Abstract
Disclosed are a real number M-ary signal encoding method, where M is a real number having N time dimensions and L frequency dimensions, and an encoding apparatus using the encoding method. The real number M-ary encoding apparatus according to the present invention comprises a coding unit which codes every K (K is an integer) binary bit units of binary data DATA to generate a first input code and a second input code, a first signal generator which receives the first input code and generates N1 number of M1-ary signals, a second signal generator which receives the second input code and generates N2 number of M2-ary signals, and a first time division multiplexing module which temporally multiplexes the N1 number of M1-ary signals and the N2 number of M2-ary signals to generate a real number M-ary signal which utilizes a voltage ratio a (a=A2/A1) used for M1-ary and M2-ary signals to minimize a transmission error rate.
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Citations
28 Claims
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1. An M-ary encoding apparatus, comprising:
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a coding unit configured to code, from binary data, to generate a first coded sequence and a second coded sequence, the coding unit including a serial-parallel converter configured to convert serial binary data to K-bit parallel data and a symbol mapper configured to map the K-bit parallel data to the first coded sequence and the second coded sequence; a signal generator configured to generate;
(1) from the first coded sequence, a first number of M1-ary signals; and
(2) from the second coded sequence, a second number of M2-ary signals; anda multiplexer configured to multiplex the first number of M1-ary signals and the second number of M2-ary signals to generate a multiplexed M-ary signal, where M1 and M2 are integers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An M-ary encoding method, the method comprising:
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coding, from binary data, to generate a first coded sequence and a second coded sequence by converting serial binary data to K-bit parallel data and mapping, by a symbol mapper, the K-bit parallel data to the first coded sequence and the second coded sequence; generating;
(1) from the first coded sequence, a first number of M1-ary signals; and
(2) from the second coded sequence, a second number of M2-ary signals; andmultiplexing the first number of M1-ary signals and the second number of M2-ary signals to generate a multiplexed M-ary signal, where M1 and M2 are integers. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A real number M-ary encoding apparatus comprising:
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a coding unit for coding binary bit units of K bit length binary data to generate a first input code and a second input code, wherein K is an integer, the coding unit comprising a serial-parallel converter configured to convert serial binary data to parallel binary bit units of the K bit length binary data and a symbol mapper configured to map the parallel binary bit units to the first input code and the second input code; a first signal generator for receiving the first input code and generating N1 number of M1-ary signals; a second signal generator for receiving the second input code and generating N2 number of M2-ary signals; and a time division multiplexer for temporally multiplexing the N1 number of M1-ary signals and the N2 number of M2-ary signals to generate a real number M-ary signal, wherein N1, N2, M1, and M2 are integers, respectively.
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28. A real number M-ary encoding method comprising:
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coding binary bit units of K bit length binary data, wherein K is an integer by converting serial binary data to parallel binary bit units of the K length binary data; mapping, by a symbol mapper, the parallel binary bit units to N1 number of M1-ary signals and N2 number of M2-ary signals; and temporally multiplexing the N1 number of M1-ary signals and N2 number of M2-ary signals to generate a first real number M-ary signal, wherein N1, N2, M1, and M2 are integers, respectively.
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Specification