Display device using low capacitance bus lines having gate lines and data lines on different substrates

• US 10,281,786 B2
• Filed: 04/20/2017
• Issued: 05/07/2019
• Est. Priority Date: 04/20/2017
• Status: Active Grant

• Current Assignee: A.U. Vista Inc. (AUO Corp.)
• Original Assignee: A.U. Vista Inc. (AUO Corp.)
• Inventors: Lee, Seok-Lyul, Luo, Fang-Chen
• Primary Examiner(s): Merlin, Jessica M
• Application Number:
  US15/492,900
• Publication Number:
  US 20180307107A1
• Time in Patent Office: 747 Days
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13685 Top gates

Abstract

A display device using low capacitance bus lines having gate lines and data lines on different substrates. The display device includes a first substrate and a second substrate spaced apart from each other, and a liquid crystal layer is disposed in the cell gap between the first substrate and the second substrate. The data lines of the display device are formed on the first substrate, and the gate lines of the display device are formed on the second substrate. The data lines formed on the first substrate and the gate lines formed on the second substrate are spaced apart by a gate insulator layer and the liquid crystal layer, which increases the gap distance between the data lines and the gate lines. Accordingly, a cross capacitance between each of the data lines and each of the gate lines can be reduced.

Claims

1. A display device, comprising:

a first substrate and a second substrate spaced apart from each other, defining a cell gap therebetween;

a liquid crystal layer disposed in the cell gap between the first substrate and the second substrate and having liquid crystal molecules, the liquid crystal layer defining a plurality of pixels;

a first structure disposed on the first substrate facing the liquid crystal layer, wherein the first structure comprises;

a semiconductor layer disposed on the first substrate;

an electrode layer disposed on the semiconductor layer to form a plurality of data lines, a plurality of source electrodes and a plurality of drain electrodes for the plurality of pixels, wherein in each pixel, the source electrode is electrically connected to a corresponding one of the data lines;

a gate insulator layer disposed on the first substrate covering the semiconductor layer; and

a first transparent conductive layer disposed on the gate insulator layer to form a plurality of pixel electrodes for the plurality of pixels, wherein in each pixel, the pixel electrode is electrically connected to the drain electrode;

a second structure disposed on the second substrate facing the liquid crystal layer, wherein the second structure comprises;

a plurality of photo spacers disposed on the second substrate and extended toward the first structure; and

a plurality of gate lines respectively disposed on the second substrate; and

a plurality of gate electrodes, each corresponding to one of the plurality of pixels and disposed on a corresponding photo spacer of the corresponding pixel, directly contacting the gate insulator layer and facing the semiconductor layer of the first structure, wherein in each pixel, the corresponding gate electrode is electrically connected to a corresponding one of the gate lines;

wherein the data lines of the first structure and the gate lines of the second structure are spaced apart by the gate insulator layer and the liquid crystal layer.

2. The display device of claim 1, wherein the second structure further comprises:

a black matrix layer disposed on the second substrate; and

a color filter layer disposed on the second substrate and the black matrix layer, wherein the plurality of photo spacers and the plurality of gate lines are disposed on the color filter layer.

3. The display device of claim 1, wherein the second structure further comprises a black matrix layer disposed on the second substrate, wherein the plurality of photo spacers and the plurality of gate lines are disposed on the black matrix layer;

and

the first structure further comprises a color filter layer disposed on the first substrate and the semiconductor layer, wherein the electrode layer is disposed on the color filter layer and the semiconductor layer.

4. The display device of claim 1, wherein the first structure further comprises:

a black matrix layer disposed on the first substrate, wherein the semiconductor layer is disposed on the black matrix layer; and

a color filter layer disposed on the semiconductor layer, wherein the electrode layer is disposed on the color filter layer and the semiconductor layer.

5. The display device of claim 1, wherein the first structure further comprises:

a passivation layer disposed on the first substrate covering the first transparent conductive layer; and

a second transparent conductive layer disposed on the passivation layer to form at least one common electrode.

6. The display device of claim 1, wherein each of the gate electrodes is directly formed on the gate insulation layer as a part of the first structure.

7. The display device of claim 1, wherein a width of the gate electrode is about the same as that of a portion of the gate insulator layer covering the semiconductor layer.

8. The display device of claim 1, wherein in each pixel, the source electrode and the drain electrode are spaced apart to form a channel gap therebetween, such that the semiconductor layer is exposed in the channel gap, and the gate electrode is positioned to be substantially aligned with the semiconductor layer exposed in the channel gap.

9. The display device of claim 8, wherein an overlapping dimension of the gate electrode and the semiconductor layer exposed in the channel gap is greater than an alignment accuracy requirement value of the display device.

10. The display device of claim 1, wherein a thickness of the liquid crystal layer is about 3-4 μ

m, and a thickness of the gate insulator layer is about 0.3-0.4 μ

m.

11. A method for forming a display device, comprising:

forming a first structure on a first substrate by;

disposing a semiconductor layer on a first substrate;

disposing an electrode layer on the semiconductor layer to form a plurality of data lines, a plurality of source electrodes and a plurality of drain electrodes for a plurality of pixels of the display device, wherein in each pixel, the source electrode is electrically connected to a corresponding one of the data lines;

disposing a gate insulator layer on the first substrate covering the semiconductor layer; and

disposing a first transparent conductive layer on the gate insulator layer to form a plurality of pixel electrodes for the plurality of pixels, wherein in each pixel, the pixel electrode is electrically connected to the drain electrode;

forming a second structure on a second substrate by;

disposing a plurality of photo spacers on the second substrate; and

forming a plurality of gate lines on the second substrate;

forming a plurality of gate electrodes on the photo spacers, each of the gate electrodes corresponding to one of the plurality of pixels and disposed on a corresponding photo spacer of the corresponding pixel, wherein in each pixel, the corresponding gate electrode is electrically connected to a corresponding one of the gate lines;

positioning the first structure and the second structure to define a cell gap therebetween, wherein each of the gate electrodes is positioned to directly contact the gate insulator layer and face the semiconductor layer of the first structure; and

forming a liquid crystal layer having liquid crystal molecules in the cell gap,

wherein the data lines of the first structure and the gate lines of the second structure are spaced apart by the gate insulator layer and the liquid crystal layer.

12. The method of claim 11, further comprising:

disposing a black matrix layer on the second substrate; and

disposing a color filter layer on the second substrate and the black matrix layer, wherein the plurality of photo spacers and the plurality of gate lines are disposed on the color filter layer.

13. The method of claim 11, further comprising:

disposing a black matrix layer on the second substrate, wherein the plurality of photo spacers and the plurality of gate lines are disposed on the black matrix layer; and

disposing a color filter layer on the first substrate and the semiconductor layer, wherein the electrode layer is disposed on the color filter layer and the semiconductor layer.

14. The method of claim 11, further comprising:

disposing a black matrix layer on the first substrate, wherein the semiconductor layer is disposed on the black matrix layer;

disposing a color filter layer on the semiconductor layer, wherein the electrode layer is disposed on the color filter layer and the semiconductor layer.

15. The method of claim 11, wherein in each pixel, the source electrode and the drain electrode are spaced apart to form a channel gap therebetween, such that the semiconductor layer is exposed in the channel gap, and the gate electrode is positioned to be substantially aligned with the semiconductor layer exposed in the channel gap.

16. The method of claim 15, wherein an overlapping dimension of the gate electrode and the semiconductor layer exposed in the channel gap is greater than an alignment accuracy requirement value of the display device.

17. A display device, comprising:

a first substrate and a second substrate spaced apart from each other, defining a cell gap therebetween;

a liquid crystal layer disposed in the cell gap between the first substrate and the second substrate and having liquid crystal molecules, the liquid crystal layer defining a plurality of pixels;

a plurality of data lines formed on the first substrate and extending along a first planar direction, each electrically connected to a source electrode of a transistor of each of the plurality of pixels;

a plurality of gate lines formed on the second substrate and extending along a second planar direction substantially perpendicular to the first planar direction, each electrically connected to a gate electrode of the transistor of each of the plurality of pixels; and

a gate driver configured to provide gate signals to the plurality of gate lines;

wherein the data lines formed on the first substrate and the gate lines formed on the second substrate are spaced apart by a gate insulator layer and the liquid crystal layer along a third direction substantially perpendicular to the first planar direction and the second planar direction.

18. The display device of claim 17, wherein the transistor of each of the plurality of pixels comprises:

the source electrode disposed on the first substrate and a semiconductor layer and electrically connected to a corresponding data line, wherein the semiconductor layer is disposed on the first substrate;

a drain electrode disposed on the first substrate and the semiconductor layer; and

the gate electrode directly contacting the gate insulator layer and facing a semiconductor layer;

wherein the source electrode and the drain electrode are spaced apart to form a channel gap therebetween, such that the semiconductor layer is exposed in the channel gap, and the gate electrode is positioned to be substantially aligned with the semiconductor layer exposed in the channel gap.

19. The display device of claim 18, further comprising:

a plurality of photo spacers disposed on the second substrate and extended toward the first substrate, wherein the gate electrode of the transistor of each of the plurality of pixels is disposed on a corresponding one of the photo spacers.

20. The display device of claim 19, wherein in each pixel, the gate electrode of the transistor is electrically connected to one of the gate lines via an electrical connecting portion disposed on the corresponding photo spacer.