Processor having accelerated user responsiveness in constrained environment
First Claim
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1. A processor comprising:
- at least one core to execute instructions; and
a power controller coupled to the at least one core, the power controller including a first logic to cause the at least one core to exit an idle state and directly enter into a maximum performance state having a maximum frequency for a first time duration to execute a responsiveness workload in which user interaction with a computer system including the processor occurs, thereafter enter into an intermediate performance state for a second time duration, and thereafter enter into a sustained performance state.
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Abstract
In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.
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Citations
22 Claims
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1. A processor comprising:
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at least one core to execute instructions; and a power controller coupled to the at least one core, the power controller including a first logic to cause the at least one core to exit an idle state and directly enter into a maximum performance state having a maximum frequency for a first time duration to execute a responsiveness workload in which user interaction with a computer system including the processor occurs, thereafter enter into an intermediate performance state for a second time duration, and thereafter enter into a sustained performance state. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
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causing at least one core of a processor to exit an idle state and directly enter into a maximum performance state for a first duration, responsive to identification of a responsiveness workload to be executed in response to a user interaction with the machine; after the first duration, causing the at least one core to enter into a second performance state until a first budget is consumed, the second performance state greater than a sustained performance state and less than the maximum performance state; and after the first budget is consumed, causing the at least one core to enter into the sustained performance state. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A system comprising:
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a processor including a plurality of cores and a power controller, responsive to identification of a user workload comprising a responsiveness workload in response to a user interaction with the system, to cause at least a first core of the plurality of cores to exit an idle state and enter into a maximum performance state for a first time duration indicated in a configuration register, thereafter enter into a plurality of intermediate performance states according to an exponential decay function, and thereafter enter into a sustained performance state; and a dynamic random access memory coupled to the processor. - View Dependent Claims (20, 21, 22)
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Specification