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Processor having accelerated user responsiveness in constrained environment

  • US 10,281,975 B2
  • Filed: 06/23/2016
  • Issued: 05/07/2019
  • Est. Priority Date: 06/23/2016
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • at least one core to execute instructions; and

    a power controller coupled to the at least one core, the power controller including a first logic to cause the at least one core to exit an idle state and directly enter into a maximum performance state having a maximum frequency for a first time duration to execute a responsiveness workload in which user interaction with a computer system including the processor occurs, thereafter enter into an intermediate performance state for a second time duration, and thereafter enter into a sustained performance state.

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