Adaptive wear levelling

• US 10,282,111 B2
• Filed: 10/21/2016
• Issued: 05/07/2019
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Barndt, Richard David, Cometti, Aldo G., Kayser, Scott Thomas
• Primary Examiner(s): Yi, David
• Assistant Examiner(s): Goldschmidt, Craig S
• Application Number:
  US15/331,552
• Publication Number:
  US 20180032268A1
• Time in Patent Office: 928 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.

Claims

1. A device comprising:

at least one processor configured to;

utilize sets of blocks of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the flash memory circuits and at least some of the blocks of at least some of the sets of blocks being marked active, wherein the at least some of the blocks of the at least some of the sets of blocks that are marked as active are utilized for the data storage operations;

monitor quality metrics of each block of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks that are marked as active are utilized for the data storage operations;

determine when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality level;

mark the one of the blocks of the one of the sets of blocks as temporarily inactive, wherein the one of the blocks of the one of the sets of blocks is not utilized for the data storage operations while marked temporarily inactive;

determine that at least one criterion is satisfied when a number of the blocks of the one of the sets of blocks that are marked as active falls below a minimum number of active blocks for a code rate associated with the one of the sets of blocks, wherein each of the sets of blocks is associated with the code rate; and

when the at least one criterion is satisfied, mark the one of the blocks of the one of the sets of blocks as active, wherein the one of the blocks of the one of the sets of blocks is again utilized for the data storage operations while marked as active.

2. The device of claim 1, wherein the at least one processor is further configured to:

responsive to determining that the criterion is satisfied, decrease the code rate associated with the one of the sets of blocks; and

responsive to decreasing the code rate, mark any blocks of the one of the sets of blocks that are marked as temporarily inactive as active, wherein any blocks of the one of the sets of blocks that are marked as active are again utilized for the data storage operations.

3. The device of claim 2, wherein the minimum number of active blocks for the code rate is less than another minimum number of active blocks for the decreased code rate.

4. The device of claim 2, wherein the at least one processor is further configured to:

determine that the at least one criterion is satisfied when a current storage capacity across all of the sets of blocks falls below a minimum storage capacity;

responsive to determining that the criterion is satisfied, identifying at least one of the sets of blocks for which at least one block is marked temporarily inactive;

decrease the code rate associated with the identified at least one of the sets of blocks; and

responsive to decreasing the code rate, mark any blocks of the at least one of the sets of blocks that are marked as temporarily inactive as active, wherein any blocks of the at least one of the sets of blocks that are marked as active are again utilized for the data storage operations.

5. The device of claim 4, Wherein the at least one processor is further configured to:

repeat the identifying, decreasing, and marking until the current storage capacity across all of the set of blocks exceeds the minimum storage capacity.

6. The device of claim 4, wherein the at least one processor is further configured to:

determine the current storage capacity based at least in part on a number of blocks of each of the sets of blocks that are marked active and the code rate associated with each of the sets of blocks.

7. The device of claim 4, wherein the at least one processor is further configured to:

identify the at least one of the sets of blocks for which at least one block is marked temporarily inactive by determining that the at least one of the sets of blocks comprises a largest number of temporarily inactive blocks relative to others of the sets of blocks.

8. The device of claim 1, wherein east one processor is further configured to:

relocate any valid data in the one of the blocks of the one of the sets of blocks before marking the one of the blocks of the one of the sets of blocks as temporarily inactive.

9. The device of claim 1, wherein the device further comprises at least one random access memory circuit and the flash memory circuits, the blocks comprise physical blocks of the flash memory circuits, and the at least one processor is further configured to:

utilize the sets of the blocks of the flash memory circuits to perform the data storage operations as indicated by a host device; and

maintain a data structure stored in the at least one random access memory circuit, wherein the data structure comprises a status of each block of each of the sets of blocks, the status of each block of each of the sets of blocks indicating at least if each block of each of the sets of blocks is marked active or is marked temporarily inactive.

10. The device of claim 1, wherein the quality comprises at least one of an error count, an error rate, or a time to program.

11. The device of claim 1, wherein the at least one processor is configured to:

arrange the blocks of the flash memory circuits into the sets of blocks.

12. A method comprising:

utilizing sets of blocks of a plurality of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the plurality of flash memory circuits and at least some of the blocks of at least some of the sets of blocks being marked active, wherein the at least some of the blocks of the at least some of the sets of blocks that are marked as active are utilized for the data storage operations;

monitoring a remaining cycle count of each of the blocks of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks that are marked as active are utilized for the data storage operations, wherein the remaining cycle count of each of the blocks of each of the sets of blocks is based at least in part on an expected cycle count associated with each of the plurality of flash memory circuits containing each of the blocks of each of the sets of blocks;

when the remaining cycle count of one of the blocks of one of the sets of blocks satisfies at least one first criterion, marking the one of the blocks of the one of the sets of blocks as temporarily inactive, wherein the one of the blocks of the one of the sets of blocks is not utilized for the data storage operations while marked temporarily inactive;

determine that at least one second criterion is satisfied when a number of the blocks of one of the sets of blocks that are marked as active falls below a minimum number of active blocks for a code rate associated with the one of the sets of blocks, wherein each of the sets of blocks is associated with the code rate; and

when the at least one second criterion is satisfied, mark the one of the blocks of the one of the sets of blocks as active, wherein the one of the blocks of the one of the sets of blocks is again utilized for the data storage operations while marked as active.

13. The method of claim 12, wherein the remaining cycle count of the one of the blocks of the one of the sets of blocks satisfies the at least one first criterion when the remaining cycle count of the one of the blocks of the one of the sets of blocks differs from another remaining cycle count of another one of the blocks of the one of the sets of blocks by a threshold number of cycles.

14. The method of claim 13, further comprising:

determining that the at least one second criterion is satisfied when the remaining cycle count associated with the one of the blocks of the one of the sets of blocks equals the another remaining cycle count associated with the another one of the blocks of the one of the sets of blocks.

15. The method of claim 12, further comprising:

prior to utilizing any of the blocks of any of the sets of blocks for reading or writing operations, cycling a respective block of each of the plurality of flash memory circuits until a respective quality metric of the respective block of each of the plurality of flash memory circuits falls below a minimum quality level;

determining the expected cycle count for each of the plurality of flash memory circuits based at least in part on a number of rapid cycles utilized to cause the respective quality metric of the respective block of each of the plurality of flash memory circuits to fall below the minimum quality level; and

storing the expected cycle count for each of the plurality of flash memory circuits in association with each of the blocks of each of the plurality of flash memory circuits.

16. The method of claim 15, further comprising:

marking the respective block of each of the plurality of flash memory circuits as inactive after cycling the respective block of each of the plurality of flash memory circuits.

17. The method of claim 15, further comprising:

determining the remaining cycle count for each of the blocks of each of the sets of blocks based at least in part on the expected cycle count associated with each of the blocks of each of the sets of blocks and a number of cycles utilized for the data storage operations for each of the blocks of each of the sets of blocks.

18. The method of claim 12, further comprising:

determining that the at least one second criterion is satisfied when a current storage capacity across all of the sets of blocks fails below a minimum storage capacity.

19. A computer program product comprising code stored in a non-transitory computer-readable storage medium, the code comprising:

code to utilize sets of blocks of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the flash memory circuits and at least some of the blocks of at least some of the sets of blocks being marked active, wherein the at least some of the blocks of the at least some of the sets of blocks that are marked as active are utilized for the data storage operations;

code to monitor quality metrics of each block of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks that are marked as active are utilized for the data storage operations;

code to determine when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality level;

code to mark the one of the blocks of the one of the sets of blocks as temporarily inactive, wherein the one of the blocks of the one of the sets of blocks is not utilized for the data storage operations while marked temporarily inactive;

code to determine that at least one criterion is satisfied when a number of the blocks of the one of the sets of blocks that are marked as active falls below a minimum number of active blocks for a code rate associated with the one of the sets of blocks, wherein each of the sets of blocks is associated with the code rate; and

code to mark the one of the blocks of the one of the sets of blocks as active, when the at least one criterion is satisfied, wherein the one of the blocks of the one of the sets of blocks is again utilized for the data storage operations while marked as active.

20. The computer program product of claim 19, wherein the code further comprises:

code to, when the criterion is satisfied, decrease the code rate associated with the one of the sets of blocks; and

code to, when the code rate has been decreased, mark any blocks of the one of the sets of blocks that are marked as temporarily inactive as active, wherein any blocks of the one of the sets of blocks that are marked as active are again utilized for the data storage operations.

21. A system comprising:

a plurality of flash memory circuits each comprising blocks;

a random access memory (RAM) configured to store a data structure that comprises a status of each of the blocks of each of the plurality of flash memory circuits, the status of each of the blocks of each of the plurality of flash memory circuits indicating at least if each of the blocks of each of the plurality of flash memory circuits is marked active or is marked temporarily inactive;

an interface communicatively coupled to a host device; and

a controller configured to;

utilize sets of the blocks of the plurality of flash memory circuits for data storage operations indicated by the host device, each of the sets of the blocks including at least one block from each of the plurality of flash memory circuits and at least some of the blocks of at least some of the sets of the blocks being marked active in the data structure, wherein the at least some of the blocks of the at least some of the sets of the blocks that are marked as active in the data structure are utilized for the data storage operations;

monitor a quality metric of each of the blocks of each of the sets of the blocks while the at least some of the blocks of the at least some of the sets of the blocks that are marked as active in the data structure are utilized for the data storage operations;

determine when the quality metric of one of the blocks of one of the sets of the blocks falls below a minimum quality level;

mark the one of the blocks of the one of the sets of the blocks as temporarily inactive the data structure, wherein the one of the blocks of the one of the sets of the blocks is not utilized for the data storage operations while marked temporarily inactive in the data structure;

determine that at least one criterion is satisfied when a number of the blocks of the one of the sets of the blocks that are marked as active falls below a minimum number of active blocks for a code rate associated with the one of the sets of the blocks, wherein each of the sets of the blocks is associated with the code rate; and

when the at least one criterion is satisfied, mark the one of the blocks of the one of the sets of the blocks as active in the data structure, wherein the one of the blocks of the one of the sets of the blocks is again utilized for the data storage operations while marked as active in the data structure.