Buffer, semiconductor apparatus and semiconductor system using the same

• US 10,282,167 B2
• Filed: 11/13/2015
• Issued: 05/07/2019
• Est. Priority Date: 07/27/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Hwang, Jin Ha, Kwon, Dae Han
• Primary Examiner(s): Geib, Benjamin P
• Assistant Examiner(s): Yimer, Getente A
• Application Number:
  US14/940,309
• Publication Number:
  US 20170031653A1
• Time in Patent Office: 1,271 Days
• Field of Search: 710 53
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A buffer may include a first sensing unit configured to sense data, and a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit. The buffer may include an equalization delay compensation unit configured to compensate the equalization control signals for signal processing delay times of the equalization control signals, and generate delay-compensated equalization control signals. The buffer may include a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals.

Claims

1. A buffer of a semiconductor apparatus comprising:

a first sensing unit configured to sense data input from an outside of the semiconductor apparatus;

a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit;

an equalization delay compensation unit configured to generate delay-compensated equalization control signals by compensating the equalization control signals for signal processing delay times of the equalization control signals; and

a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals,

wherein the noise removal unit is coupled between the first sensing unit and the second sensing unit in parallel.

2. The buffer according to claim 1, wherein the signal processing delay times of the equalization control signals correspond to signal processing delay times from output terminals of the first sensing unit to output terminals of the second sensing unit.

3. The buffer according to claim 1, wherein the second sensing unit comprises:

an amplification section configured to amplify the outputs of the first sensing unit;

a slicer configured to convert an output of the amplification section into a level capable of being processed inside a semiconductor apparatus; and

a driver configured to drive an output of the slicer, and output the equalization control signals.

4. The buffer according to claim 1, wherein the equalization delay compensation unit comprises:

first and second variable resistors having respective one ends coupled with a power supply terminal;

a first transistor coupled with the first variable resistor, and having a gate configured to receive any one of the equalization control signals;

a second transistor coupled with the second variable resistor, and having a gate configured to receive the other one of the equalization control signals; and

a variable capacitor coupled between a node where the first variable resistor and the first transistor are coupled and a node where the second variable resistor and the second transistor are coupled.

5. The buffer according to claim 1,

wherein the equalization delay compensation unit comprises:

first and second variable resistors having respective one ends coupled with a power supply terminal;

a first transistor coupled with the first variable resistor, and having a gate configured to receive any one of the equalization control signals;

a second transistor coupled with the second variable resistor, and having a gate configured to receive the other one of the equalization control signals; and

a variable capacitor coupled between a node where the first variable resistor and the first transistor are coupled and a node where the second variable resistor and the second transistor are coupled, and

wherein the equalization delay compensation unit is configured to compensate the equalization control signals for the signal processing delay times of the equalization control signals, by controlling resistance values of the first and second variable resistors and a capacitance value of the variable capacitor.

6. The buffer according to claim 1, wherein the noise removal unit comprises:

a first filter configured to primarily remove noise of the output signals of the first sensing unit, according to the equalization control signals; and

a second filter configured to secondarily remove noise of the output signals of the first sensing unit, according to the delay-compensated equalization control signals.

7. The buffer according to claim 1, wherein the noise removal unit comprises:

a finite impulse response (FIR) filter configured to primarily remove a portion of intersymbol interference (ISI) of the output signals of the first sensing unit, according to the equalization control signals; and

a infinite impulse response IIR filter configured to secondarily remove a residual component of the ISI of the output signals of the first sensing unit, according to the delay-compensated equalization control signals.

8. The buffer according to claim 7, wherein the FIR filter comprises a 1-tap FIR filter.

9. A semiconductor apparatus comprising:

a core block including a cell array;

a first buffer configured to sense data input from an outside of the semiconductor apparatus, primarily remove noise of sensed signals according to equalization control signals, and secondarily remove noise of the sensed signals according to delay-compensated equalization control signals;

a data path coupled with the first buffer;

a second buffer configured to sense a data strobe signal;

a strobe signal path coupled with the second buffer;

a latch block configured to latch data having passed through the data path, according to the data strobe signal having passed through the strobe signal path, and provide resultant data to the core block, and

the first buffer further comprising;

a noise removal unit;

a first sensing unit; and

a second sensing unit,

wherein the noise removal unit is coupled between the first sensing unit and the second sensing unit in parallel.

10. The semiconductor apparatus according to claim 9, wherein the semiconductor apparatus is a matched delay type in which respective delay times of the data path and the strobe signal path are controlled such that the data and the data strobe signal are provided to the latch block at the same time.

11. The semiconductor apparatus according to claim 9, wherein the first buffer includes an IIR (infinite impulse response) filter and is configured to perform an equalization function by using an IIR filter.

12. The semiconductor apparatus according to claim 9, wherein the first buffer comprises:

a first sensing unit configured to sense the data;

a second sensing unit configured to generate the equalization control signals according to outputs of the first sensing unit;

an equalization delay compensation unit configured to generate the delay-compensated equalization control signals by compensating the equalization control signals for signal processing delay times of the equalization control signals; and

a noise removal unit configured to primarily remove noise of the output signals of the first sensing unit according to the equalization control signals, and secondarily remove noise of the output signals of the first sensing unit according to the delay-compensated equalization control signals,

wherein the noise removal unit is coupled between the first sensing unit and the second sensing unit in parallel.

13. The semiconductor apparatus according to claim 12, wherein the signal processing delay times of the equalization control signals correspond to signal processing delay times from output terminals of the first sensing unit to output terminals of the second sensing unit.

14. The semiconductor apparatus according to claim 12, wherein the equalization delay compensation unit comprises:

first and second variable resistors having respective one ends coupled with a power supply terminal;

a first transistor coupled with the first variable resistor, and having a gate configured to receive any one of the equalization control signals;

a second transistor coupled with the second variable resistor, and having a gate configured to receive the other one of the equalization control signals; and

a variable capacitor coupled between a node where the first variable resistor and the first transistor are coupled and a node where the second variable resistor and the second transistor are coupled.

15. The semiconductor apparatus according to claim 12,

wherein the equalization delay compensation unit comprises:

first and second variable resistors having respective one ends coupled with a power supply terminal;

a first transistor coupled with the first variable resistor, and having a gate configured to receive any one of the equalization control signals;

a second transistor coupled with the second variable resistor, and having a gate configured to receive the other one of the equalization control signals; and

a variable capacitor coupled between a node where the first variable resistor and the first transistor are coupled and a node where the second variable resistor and the second transistor are coupled, and

wherein the equalization delay compensation unit is configured to compensate the equalization control signals for the signal processing delay times of the equalization control signals, by controlling resistance values of the first and second variable resistors and a capacitance value of the variable capacitor.

16. The semiconductor apparatus according to claim 12, wherein the noise removal unit comprises:

a first filter configured to primarily remove noise of the output signals of the first sensing unit, according to the equalization control signals; and

a second filter configured to secondarily remove noise of the output signals of the first sensing unit, according to the delay-compensated equalization control signals.

17. The semiconductor apparatus according to claim 12, wherein the noise removal unit comprises:

a finite impulse response (FIR) filter configured to primarily remove a portion of inter symbol interference (ISI) of the output signals of the first sensing unit, according to the equalization control signals; and

a infinite impulse response (IIR) filter configured to secondarily remove a residual component of the ISI of the output signals of the first sensing unit, according to the delay-compensated equalization control signals.

18. The semiconductor apparatus according to claim 17, wherein the FIR filter comprises a 1-tap FIR filter.

19. A buffer of a semiconductor apparatus comprising:

a first sensing unit configured to sense data input from an outside of the semiconductor apparatus;

a second sensing unit configured to generate equalization control signals according to outputs of the first sensing unit;

an equalization delay compensation unit configured to generate delay-compensated equalization control signals by compensating the equalization control signals for signal processing delay times of the equalization control signals; and

a noise removal unit configured to remove noise of the output signals of the first sensing unit according to the equalization control signals and the delay-compensated equalization control signals,

wherein the noise removal unit is coupled between the first sensing unit and the second sensing unit in parallel.

20. The buffer according to claim 19, wherein the equalization delay compensation unit comprises:

first and second variable resistors having respective one ends coupled with a power supply terminal;

a variable capacitor coupled between other ends of the first and second variable resistors, and

wherein the equalization delay compensation unit is configured to compensate the equalization control signals for the signal processing delay times of the equalization control signals, by controlling resistance values of the first and second variable resistors and a capacitance value of the variable capacitor.

21. The buffer according to claim 19, wherein the noise removal unit first removes noise of the output signals of the first sensing unit with a first filter and then secondarily removes noise of the output signals of the first sensing unit with a second filter.