Hierarchical lossless compression and null data support

• US 10,282,808 B2
• Filed: 05/27/2016
• Issued: 05/07/2019
• Est. Priority Date: 05/27/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Seiler, Larry, Surti, Prasoonkumar, Navale, Aditya
• Primary Examiner(s): Beutel, William A
• Application Number:
  US15/167,987
• Publication Number:
  US 20170345122A1
• Time in Patent Office: 1,075 Days
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/302 In image processor or graphics adapter
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management

Abstract

Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More particularly, one or more implementations described herein facilitates hierarchical lossless compression of memory with null data support for memory resources, including texture maps. More particularly still, one or more implementations described herein facilitates the use of meta-data for lossless compression and the support of null encodings for Tiled Resources. This technology also permits use of the fast-clear compression method, where meta-data specifies that the entire access should return some specified clear value.

Claims

1. A graphics processor comprising:

a memory; and

one or more graphics cores configured to operate with the memory to process computer graphics by;

receiving an access request to a memory resource that is associated with a metadata stored in the memory, the metadata being configured to encode, as a number of bits per respective compression block, state data identifying (i) when the associated memory resource is null, a null-state indicator value so indicating, and (ii) when the associated memory resource is not null, a compression state of the respective compression block from among possible different compression states;

determining whether the state data encodes the null-state indicator value indicating that the associated memory resource is null before accessing the memory resource; and

in response to (i) the null-state determination, and (ii) the access request being a write operation, ignoring the access request.

2. The graphics processor as recited in claim 1, wherein the one or more graphics cores are configured to, in response to (i) the null-state determination and (ii) the access request being a read operation, return a default value as a response to the access request.

3. The graphics processor as recited in claim 1, wherein the memory resource is a cache, and the ignoring of the access request includes marking a cacheline of the cache as null.

4. The graphics processor as recited in claim 1, wherein:

the memory resource is a cache,

the ignoring of the access request includes marking a cacheline of the cache as null,

the access request is a write request, and

the one or more graphics cores are configured to;

read a null-state on the memory resource; and

in response to reading of the null-state, (i) returning an indication that the memory resource contains one or more null addresses, (ii) storing a default value in a cacheline, and (iii) setting a state in a cache that prevents writes to the cacheline.

5. The graphics processor as recited in claim 4, wherein the default value is a defined value that is indicative of a null state.

6. The graphics processor as recited in claim 4, wherein the default value is zero.

7. The graphics processor as recited in claim 1, wherein the number of bits of state data per respective compression block encoded as the metadata is M bits per compression block and indicates a compression state from among (2^M−

1) possible different compression states.

8. The graphics processor as recited in claim 1, wherein the one or more graphics cores are configured to, in response to the null determination and the access request being a fast clear operation, ignore the access request.

9. The graphics processor as recited in claim 1, wherein the one or more graphics cores are configured to set the null-state indicator value of the metadata to indicate that the associated memory resource is null in response to (i) an initialization of the memory resource or (ii) the memory resource being unmapped from memory.

10. The graphics processor as recited in claim 1, wherein the one or more graphics cores are configured to set the null-state indicator value of the metadata to indicate that the associated memory resource is not null in response to the memory resource being mapped to memory.

15. The graphics processor of claim 1, wherein the possible different compression states associated with the respective compression block is based upon the number of bits encoded by the metadata.

16. The graphics processor of claim 1, wherein the metadata is hierarchical.

11. A graphics processor comprising:

a memory; and

one or more graphics cores configured to operate with the memory to process computer graphics by;

receiving an access request to a memory resource that is associated with a metadata stored in the memory, the metadata being configured to encode, as a number of bits per respective compression block, state data identifying (i) when the associated memory resource is null, a null-state indicator value so indicating, and (ii) when the associated memory resource is not null, a compression state of the respective compression block from among possible different compression states;

determining whether the data of the memory resource is in a null state by accessing the state data associated with the memory resource without performing a read operation of the memory resource;

in response to (i) the null state determination, and (ii) the access request being a read operation, returning a default value in response to the access request instead of reading the memory resource; and

receiving another access request to the memory resource that is a write operation and, in response to (i) the null state determination, and (ii) the another access request being a write operation, ignoring the write operation access request.

12. The graphics processor as recited in claim 11, wherein the memory resource is a cache.

13. The graphics processor as recited in claim 11, wherein the default value is a defined value that is indicative of the null state.

14. The graphics processor as recited in claim 11, wherein the default value is zero.

17. A non-transitory computer-readable medium having instructions stored thereon that, when executed by one of more processors, cause the one or more processors to:

receive an access request to a memory resource that is associated with a metadata stored in a memory, the metadata being configured to encode, as a number of bits per respective compression block, state data identifying (i) when the associated memory resource is null, a null-state indicator value so indicating, and (ii) when the associated memory resource is not null, a compression state of the respective compression block from among possible different compression states;

determine whether the data of the memory resource is in a null state by accessing the state data associated with the memory resource without performing a read operation of the memory resource; and

in response to (i) the null state determination, and (ii) the access request being a write operation, ignoring the access request.

18. The non-transitory computer-readable medium of claim 17, further including instructions that, when executed by the one of more processors, cause the one or more processors to:

receive another access request to the memory resource that is a read operation, and returning a default value as a response to the access request instead of reading the memory resource.

19. The non-transitory computer-readable medium of claim 17, wherein the default value is a defined value that is indicative of the null state.