Digital architecture with merged non-linear emission clock signals for a display panel

• US 10,283,037 B1
• Filed: 08/26/2016
• Issued: 05/07/2019
• Est. Priority Date: 09/25/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Far, Mohammad B. Vahid, Bae, Hopil, Nho, Hyunwoo, Lu, Xiang
• Primary Examiner(s): Zhou, Hong
• Application Number:
  US15/249,283
• Time in Patent Office: 984 Days
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2320/0285 using tables for spatial correction of display data
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2088 with use of a plurality of processors, each processor controlling a number of individual elements of the matrix
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]

Abstract

Systems and apparatuses provide a digital architecture with merged non-linear emission clocks for a display panel. In one embodiment, a display driver hardware circuit includes decoder logic to store a mapping between a plurality of non-linear gray scale clock signals and a merged non-linear gray scale clock signal that represents a combination of the plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals. In one example, the first non-linear gray scale clock signal is associated with at least one display element of a first color and the second non-linear gray scale clock signal is associated with at least one display element of a second color. A driver circuitry is coupled to the decoder logic. The driver circuitry includes a counter to store a number of pulses of the merged non-linear gray scale clock signal and driving circuitry to cause emission of the at least one display element of a first color based on the first non-linear gray scale clock signal.

Claims

1. A display driver hardware circuit comprising:

decoder logic to store a mapping between a plurality of non-linear gray scale clock signals and a merged non-linear gray scale clock signal that represents a combination of the plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals with the first non-linear gray scale clock signal being associated with at least one display element of a first color and the second non-linear gray scale clock signal being associated with at least one display element of a second color; and

driver circuitry coupled to the decoder logic, the driver circuitry includes a counter to store a number of pulses of the merged non-linear gray scale clock signal and driving circuitry to cause emission of the at least one display element of a first color based on the first non-linear gray scale clock signal.

2. The display driver hardware circuit of claim 1, wherein the first and second non-linear gray scale clock signals to each be represented with a first number of bits and the merged non-linear gray scale clock signal to be represented with a second number of bits.

3. The display driver hardware circuit of claim 1, wherein the driver circuitry further comprises:

a data register to store a modified data signal having a first set of data and a second set of data; and

a comparator to compare the modified data signal from the data register to a number of pulses of the merged non-linear clock signal, wherein the driving circuitry, in response to output of the comparator, to cause the emission of the at least one display element of a first color and to cause an emission of the at least one display element of a second color.

4. The display driver hardware circuit of claim 1, wherein the plurality of non-linear gray scale clock signals further includes a third non-linear gray scale clock signal that is associated with a display element of a third color.

5. The display driver hardware circuit of claim 4, wherein the merged non-linear gray scale clock signal further includes pulses of the third non-linear gray scale clock signal.

6. The display driver hardware circuit of claim 1, wherein adjacent display elements are multiple rows and multiple columns of a display panel.

7. A micro-driver hardware circuit comprising:

a counter to receive a merged non-linear gray scale clock signal that represents a combination of a plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals with each of the first and second clock signals being associated with a different color of display elements, the counter to store a number of pulses of the merged non-linear gray scale clock signal; and

driving circuitry coupled to the counter, the driving circuitry to cause emissions of the display elements based on the merged non-linear gray scale clock signal.

8. The micro-driver hardware circuit of claim 7, wherein the first and second non-linear gray scale clock signals to each be represented with a first number of bits and the merged non-linear gray scale clock signal to be represented with a second number of bits.

9. The micro-driver hardware circuit of claim 7, further comprising:

a data register to store a modified data signal having at least a first set of data that is associated with the first non-linear gray scale clock signal and a second set of data that is associated with the second non-linear gray scale clock signal; and

a comparator to compare the modified data signal from the data register to a number of pulses of the merged non-linear clock signal, wherein the driving circuitry, in response to output of the comparator, to cause an emission of at least one display element of a first color based on the first set of data and to cause an emission of at least one display element of a second color based on the second set of data.

10. The micro-driver hardware circuit of claim 7, wherein the plurality of non-linear gray scale clock signals further includes a third non-linear gray scale clock signal that is associated with a display element of a third color.

11. The micro-driver hardware circuit of claim 10, wherein the merged non-linear gray scale clock signal further includes pulses of the third non-linear gray scale clock signal.

12. A method to drive a display panel comprising:

counting a number of pulses of a merged non-linear gray scale clock that represents a combination of a plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals with each of the first and second clock signals being associated with a different color of display elements of the display panel;

storing a modified data signal having a first set of data that is associated with the first non-linear gray scale clock signal and storing a second set of data that is associated with the second non-linear gray scale clock signal in a data register; and

comparing the modified data signal from the data register to a number of pulses of the merged non-linear clock signal.

13. The method of claim 12, further comprising:

causing an emission of at least one display element of a first color based on the first set of data; and

causing an emission of at least one display element of a second color based on the second set of data.

14. The method of claim 12, wherein the first and second non-linear gray scale clock signals to each be represented with a first number of bits and the merged non-linear gray scale clock signal to be represented with a second number of bits.

15. The method of claim 12, further comprising:

modifying a data signal that is represented with a first number of bits into the modified data signal that is represented with a second number of bits in order to identify the first set of data and the second set of data.

16. The method of claim 12, wherein the plurality of non-linear gray scale clock signals further includes a third non-linear gray scale clock signal that is associated with a display element of a third color.

17. A display system comprising:

row selection logic to select a number of rows in an emission group of display elements of a display panel;

decoder logic to store a mapping between a plurality of non-linear gray scale clock signals and a merged non-linear gray scale clock signal that represents a combination of the plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals with each of the first and second clock signals being associated with a different color of display elements; and

driver circuitry coupled to the decoder logic, the driver circuitry includes a counter to store a number of pulses of the merged non-linear gray scale clock signal and driving circuitry to cause emissions of the display elements based on the merged non-linear gray scale clock signal.

18. The display system of claim 17, wherein the first and second non-linear gray scale clock signals to each be represented with a first number of bits and the merged non-linear gray scale clock signal to be represented with a second number of bits.

19. The display system of claim 17, wherein the driver circuitry further comprises:

a data register to store a modified data signal having a first set of data and a second set of data;

a comparator to compare the modified data signal from the data register to a number of pulses of the merged non-linear clock signal, wherein the driving circuitry, in response to output of the comparator, to cause an emission of at least one display element of a first color and to cause an emission of at least one display element of a second color.

20. The display system of claim 17, wherein the plurality of non-linear gray scale clock signals further includes a third non-linear gray scale clock signal that is associated with a display element of a third color.

21. The display system of claim 17, wherein the row selection logic receives the merged non-linear gray scale clock signal and sends the merged non-linear gray scale clock signal to the driver circuitry.

22. A driver circuitry comprising:

logic to receive a merged non-linear clock signal, the logic for separating or extracting a plurality of non-linear clocks signals including first and second non-linear clock signals that have been merged into the merged non-linear clock signal; and

a counter coupled to the logic, the counter to receive the second non-linear clock signal or a clock signal that is based on the second non-linear clock signal, the counter to store a number of pulses of the second non-linear clock signal or the clock signal that is based on the second non-linear clock signal; and

a comparator coupled to the counter, the comparator to compare a data signal to a number of pulses of the second non-linear clock signal or the clock signal that is based on the second non-linear clock signal.

23. The driver circuitry of claim 22, further comprising:

a driving circuitry coupled to the comparator, the driving circuitry, in response to output of the comparator, to cause emissions of at least one display element of a second color that is associated with the second non-linear clock signal.

24. The driver circuitry of claim 22, wherein the logic includes a delay cell to delay the merged clock signal and to generate a delayed clock signal.

25. The driver circuitry of claim 22, wherein the logic includes a logic function to be applied to the merged clock signal and the delayed clock signal, the logic function generates the second non-linear clock signal or a clock signal that is based on the second non-linear clock signal, wherein the second non-linear clock signal is associated with at least one display element of a second color.

26. The driver circuitry of claim 25, wherein the plurality of non-linear gray scale clock signals further includes a third non-linear gray scale clock signal that is associated with a display element of a third color.