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Digital architecture with merged non-linear emission clock signals for a display panel

  • US 10,283,037 B1
  • Filed: 08/26/2016
  • Issued: 05/07/2019
  • Est. Priority Date: 09/25/2015
  • Status: Active Grant
First Claim
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1. A display driver hardware circuit comprising:

  • decoder logic to store a mapping between a plurality of non-linear gray scale clock signals and a merged non-linear gray scale clock signal that represents a combination of the plurality of non-linear gray scale clock signals including first and second non-linear gray scale clock signals with the first non-linear gray scale clock signal being associated with at least one display element of a first color and the second non-linear gray scale clock signal being associated with at least one display element of a second color; and

    driver circuitry coupled to the decoder logic, the driver circuitry includes a counter to store a number of pulses of the merged non-linear gray scale clock signal and driving circuitry to cause emission of the at least one display element of a first color based on the first non-linear gray scale clock signal.

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