Stacked die semiconductor device with separate bit line and bit line bar interconnect structures

• US 10,283,171 B2
• Filed: 03/30/2015
• Issued: 05/07/2019
• Est. Priority Date: 03/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chi, Shyh-An
• Primary Examiner(s): Lam, David
• Application Number:
  US14/673,108
• Publication Number:
  US 20160293227A1
• Time in Patent Office: 1,499 Days
• Field of Search: 365 51, 365 52, 365 63, 36523003, 365154, 365156, 365148, 257773, 257734, 257330
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An apparatus includes a first tier, a second tier and a memory. The second tier is vertically stacked on the first tier. The memory includes a column of memory bit cells. A first portion of the column of memory bit cells is on the first tier. A second portion of the column of memory bit cells is on the second tier.

Claims

1. An apparatus, comprising:

a first tier on a first substrate;

a second tier on a second substrate, wherein the second tier is vertically stacked on the first tier; and

a memory comprising a column of memory bit cells,

wherein

a first portion of the column of memory bit cells is on the first tier;

a second portion of the column of memory bit cells is on the second tier;

the first portion of the column of memory bit cells is coupled with a first segment of a first bit line; and

the second portion of the column of memory bit cells is coupled with a second segment of the first bit line.

2. The apparatus of claim 1, wherein a number of memory bit cells of the first portion of the column of memory bit cells is the same as a number of memory bit cells of the second portion of the column of memory bit cells.

3. The apparatus of claim 1, wherein

the first portion of the column of memory bit cells is coupled with a first segment of a second bit line in the first tier;

and

the second portion of the column of memory bit cells is coupled with a second segment of the second bit line in the second tier.

4. The apparatus of claim 3, wherein at least one interconnection structure includes a conductive bump which couples with the first segment of the first bit line and the second segment of the first bit line, such that the-at least one interconnection structure, the first segment of the first bit line and the second segment of the first bit line form a “

C”

shape.

5. The apparatus of claim 3, wherein at least two interconnection structures couple with the first segment of the first bit line and the second segment of the first bit line, such that the at least two interconnection structures, the first segment of the first bit line and the second segment of the first bit line form at least one quadrangle.

6. The apparatus of claim 3, wherein the second segment of the first bit line is vertically above the first segment of the first bit line.

7. The apparatus of claim 1, wherein at least one memory bit cell of the first portion of the column of memory bit cells is vertically below at least one memory bit cell of the second portion of the column of memory bit cells.

8. An apparatus, comprising:

a first tier on a first substrate;

a second tier on a second substrate and vertically stacked on the first tier; and

a column of memory bit cells;

a first bit line and a first bit line bar in the first tier; and

a second bit line and a second bit line bar in the second tier;

wherein

the second bit line is electrically coupled to the first bit line by at least one interconnection structure that includes a conductive bump to electrically connect the first substrate to the second substrate;

a first portion of the column of memory bit cells are coupled to the first bit line and the first bit line bar; and

a second portion of the column of memory bit cells are coupled to the second bit line and the second bit line bar.

9. The apparatus of claim 8, wherein

at least one interconnection structure couples with the first bit line and the second bit line;

and

at least another one interconnection structure that spans the first tier and the second tier couples with the first bit line bar and the second bit line bar.

10. The apparatus of claim 8, wherein the second bit line is vertically above the first bit line, the second bit line bar is vertically above the first bit line bar.

11. The apparatus of claim 8, wherein at least one memory bit cell of the first portion of the column of memory bit cells is vertically below at least one memory bit cell of the second portion of the column of memory bit cells.

12. An apparatus, comprising:

a peripheral tier;

a first tier on a first substrate and a second tier on a second substrate vertically stacked on the peripheral tier;

an interconnection structure that electrically connects the first substrate to the second substrate, and couples to a first bit line coupled to memory bit cells in the first tier and to a second bit line coupled to memory bit cells in the second tier; and

a plurality of memory slices, each of the plurality of memory slices comprising;

a first portion of a column of memory bit cells in the first tier; and

a second portion of the column of memory bit cells in the second tier;

wherein the peripheral tier is configured to regulate memory cell addresses by a BL-BLB pair coupled to at least one of the plurality of memory slices.

13. The apparatus of claim 12, wherein the peripheral tier is configured to regulate memory cell addresses by word lines coupled to at least one of the plurality of memory slices.

14. The apparatus of claim 13, wherein the word lines include a first word line and a second word line;

the first word line couples to at least one memory bit cells in at least one of the plurality of memory slices in the first tier; and

the second word line couples to at least one memory bit cells in at least one of the plurality of memory slices in the second tier.

15. The apparatus of claim 14, wherein a first segment of one of the first word line and the second word line is disposed to extend in a first direction, a second segment of one of the first word line and the second word line is disposed to extend in a second direction different from the first direction.

16. The apparatus of claim 15, wherein the first segment of one of the first word line and the second word line is in parallel with the BL-BLB pair.

17. The apparatus of claim 16, wherein the second segment of one of the first word line and the second word line is perpendicular to the BL-BLB pair.

18. The apparatus of claim 13, further comprising a pattern of conductive connections configured to connect with the word lines and the BL-BLB pair the conductive connections being disposed on a first substrate of the peripheral tier.

19. The apparatus of claim 18, wherein the pattern of conductive connections of the BL-BLB pair are sandwiched by the conductive connections of the word lines in a third direction.

20. The apparatus of claim 18, wherein the pattern of conductive connections of the word lines are sandwiched by the conductive connections of the BL-BLB pair in a third direction.