Data writing method, memory control circuit unit and memory storage apparatus

• US 10,283,196 B2
• Filed: 08/16/2016
• Issued: 05/07/2019
• Est. Priority Date: 06/17/2016
• Status: Active Grant

• Current Assignee: Phison Electronics Corporation
• Original Assignee: Phison Electronics Corporation
• Inventors: Yeh, Chih-Kang, Chang, Po-Yung
• Primary Examiner(s): Faal, Baboucarr
• Application Number:
  US15/238,715
• Publication Number:
  US 20170365334A1
• Time in Patent Office: 994 Days
• Field of Search: None
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0644 Management of space entities, e.g. partitions, extents, pools
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A data writing method for a rewritable non-volatile memory module is provided. The method includes grouping physical erasing units of a rewritable non-volatile memory module at least into a first area and a second area, wherein the second area is programmed with a single-page programming mode and the first area is programmed with a multi-page programming mode. The method further includes receiving first data; and determining whether the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value, and if yes, writing the first data into the physical erasing units of the second area.

Claims

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the physical erasing units are grouped at least into a first area and a second area, the number of data bits stored by each memory cell in the physical erasing units of the second area is less than the number of data bits stored by each memory cell in the physical erasing units of the first area, and the data writing method comprises:

receiving first data; and

writing the first data into at least one physical erasing unit among the physical erasing units of the second area if the number of physical erasing units having only part of physical programming units being programmed among the physical erasing units of the first area is not less than a predetermined value.

2. The data writing method of claim 1, further comprising:

determining whether the number of physical erasing units having only part of physical programming units being programmed among the physical erasing units of the first area is less than the predetermined value.

3. The data writing method of claim 1, further comprising:

writing the first data into a physical erasing unit among the physical erasing units of the first area if the number of the physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than the predetermined value.

4. The data writing method of claim 1, further comprising:

selecting a first physical erasing unit among the physical erasing units of the first area to perform a first valid data merging operation, and copying valid data in at least one second physical erasing unit among the physical erasing units of the first area to the first physical erasing unit in the first valid data merging operation,

wherein the first physical erasing unit is determined as the physical erasing unit having only part of physical programming units being programmed if the first physical erasing unit is not fully written.

5. The data writing method of claim 4, further comprising:

selecting a third physical erasing unit from among the physical erasing units of the first area if the first physical erasing unit is fully written;

copying the first data in the at least one physical erasing unit of the second area to the third physical erasing unit; and

performing an erasing operation on the at least one physical erasing unit of the second area.

6. The data writing method of claim 1, further comprising:

before the first data is received, receiving a write command and second data corresponding to the write command from a host system;

selecting a fourth physical erasing unit from among the physical erasing units of the first area; and

writing the second data into the fourth physical erasing unit,

wherein the fourth physical erasing unit is determined as the physical erasing unit having only part of physical programming units being programmed if the fourth physical erasing unit is not fully written.

7. The data writing method of claim 6, further comprising:

selecting a plurality of fifth physical erasing units among the physical erasing units of the second area to perform a second valid data merging operation;

copying valid data in at least one sixth physical erasing unit among the physical erasing units of the first area to the fifth physical erasing units, selecting a seventh physical erasing unit among the physical erasing units of the first area, and copying the valid data in the fifth physical erasing units to the seventh physical erasing unit in the second valid data merging operation; and

performing an erasing operation on the fifth physical erasing units after copying the valid data in the fifth physical erasing units to the seventh physical erasing unit.

8. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the physical erasing units are grouped at least into a first area and a second area, the number of data bits stored by each memory cell in the physical erasing units of the second area is less than the number of data bits stored by each memory cell in the physical erasing units of the first area, the memory control circuit unit comprising:

a host interface, configured to couple to a host system;

a memory interface, configured to couple to the rewritable non-volatile memory module; and

a memory management circuit, coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to receive first data,

wherein the memory management circuit is further configured to write the first data into at least one physical erasing unit among the physical erasing units of the second area if the number of physical erasing units having only part of physical programming units being programmed among the physical erasing units of the first area is not less than a predetermined value,

wherein the memory management circuit is further configured to write the first data into a physical erasing unit among the physical erasing units of the first area if the number of the physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than the predetermined value.

9. The memory control circuit unit of claim 8,

wherein the memory management circuit is further configured to determine whether the number of the physical erasing units having only part of physical programming units being programmed among the physical erasing units of the first area is less than the predetermined value.

10. The memory control circuit unit of claim 8,

wherein the memory management circuit is further configured to select a first physical erasing unit among the physical erasing units of the first area to perform a first valid data merging operation, and give a command sequence for copying valid data in at least one second physical erasing unit among the physical erasing units of the first area to the first physical erasing unit in the first valid data merging operation,

wherein the first physical erasing unit is determined as the physical erasing unit having only part of physical programming units being programmed if the first physical erasing unit is not fully written.

11. The memory control circuit unit of claim 10,

wherein the memory management circuit is further configured to select a third physical erasing unit from among the physical erasing units of the first area if the first physical erasing unit is fully written, give another command sequence for copying the first data in the at least one physical erasing unit of the second area to the third physical erasing unit, and give another command sequence for performing an erasing operation on the at least one physical erasing unit of the second area.

12. The memory control circuit unit of claim 8,

wherein before the first data is received, the memory management circuit is further configured to receive a write command and second data corresponding to the write command from the host system, select a fourth physical erasing unit from among the physical erasing units of the first area, and give another command sequence for writing the second data into the fourth physical erasing unit,

wherein the fourth physical erasing unit is determined as the physical erasing unit having only part of physical programming units being programmed if the fourth physical erasing unit is not fully written.

13. The memory control circuit unit of claim 12,

wherein the memory management circuit is further configured to select a plurality of fifth physical erasing units among the physical erasing units of the second area to perform a second valid data merging operation,

wherein the memory management circuit is further configured to give another command sequence for copying valid data in at least one sixth physical erasing unit among the physical erasing units of the first area to the fifth physical erasing units, select a seventh physical erasing unit among the physical erasing units of the first area, and give another command sequence for copying the valid data in the fifth physical erasing units to the seventh physical erasing unit in the second valid data merging operation,

wherein the memory management circuit is further configured to give another command sequence for performing an erasing operation on the fifth physical erasing units after copying the valid data in the fifth physical erasing units to the seventh physical erasing unit.

14. A memory storage apparatus comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile have a plurality of physical erasing units, the physical erasing units are grouped at least into a first area and a second area, the number of data bits stored by each memory cell in the physical erasing units of the second area is less than the number of data bits stored by each memory cell in the physical erasing units of the first area, the memory storage apparatus further comprising:

a connection interface unit, configured to couple to a host system; and

a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is configured to receive first data,

wherein the memory control circuit unit is further configured to write the first data into at least one physical erasing unit among the physical erasing units of the second area if the number of physical erasing units having only part of physical programming units being programmed among the physical erasing units of the first area is not less than a predetermined value.

15. The memory storage apparatus of claim 14,

wherein the memory control circuit unit is further configured to determine whether the number of the physical erasing units having only part of physical programming units being programmed among the physical erasing units of the first area is less than the predetermined value.

16. The memory storage apparatus of claim 14,

wherein the memory control circuit unit is further configured to write the first data into a physical erasing unit among the physical erasing units of the first area if the number of the physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than the predetermined value.

17. The memory storage apparatus of claim 14,

wherein the memory control circuit unit is further configured to select a first physical erasing unit among the physical erasing units of the first area to perform a first valid data merging operation, and copy valid data in at least one second physical erasing unit among the physical erasing units of the first area to the first physical erasing unit in the first valid data merging operation,

wherein the first physical erasing unit is determined as the physical erasing unit having only part of physical programming units being programmed if the first physical erasing unit is not fully written.

18. The memory storage apparatus of claim 17,

wherein the memory control circuit unit is further configured to select a third physical erasing unit from among the physical erasing units of the first area if the first physical erasing unit is fully written, copy the first data in the at least one physical erasing unit of the second area to the third physical erasing unit, and perform an erasing operation on the at least one physical erasing unit of the second area.

19. The memory storage apparatus of claim 14,

wherein before the first data is received, the memory control circuit unit is further configured to

receive a write command and second data corresponding to the write command from a host system, select a fourth physical erasing unit from among the physical erasing units of the first area, and write the second data into the fourth physical erasing unit,

wherein the fourth physical erasing unit is determined as the physical erasing unit having only part of physical programming units being programmed if the fourth physical erasing unit is not fully written.

20. The memory storage apparatus of claim 19,

wherein the memory control circuit unit is further configured to select a plurality of fifth physical erasing units among the physical erasing units of the second area to perform a second valid data merging operation,

wherein the memory control circuit unit copies valid data in at least one sixth physical erasing unit among the physical erasing units of the first area to the fifth physical erasing units, selects a seventh physical erasing unit among the physical erasing units of the first area, and copies the valid data in the fifth physical erasing units to the seventh physical erasing unit in the second valid data merging operation,

wherein the memory control circuit unit performs an erasing operation on the fifth physical erasing units after copying the valid data in the fifth physical erasing units to the seventh physical erasing unit.

21. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical erasing units, the physical erasing units are grouped at least into a first area and a second area, the number of data bits stored by each memory cell in the physical erasing units of the second area is less than the number of data bits stored by each memory cell in the physical erasing units of the first area, and the data writing method comprises:

receiving first data;

writing the first data into one physical erasing unit among the physical erasing units of the first area without taking a pathway via the second area if the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value; and

writing the first data into at least one physical erasing unit among the physical erasing units of the second area if the number of the physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is not less than the predetermined value.

22. A memory storage apparatus, comprising:

a connection interface unit, configured to couple to a host system;

a rewritable non-volatile memory module having a plurality of physical erasing units; and

a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,

wherein the memory control circuit unit is configured to group the physical erasing units at least into a first area and a second area, wherein the number of data bits stored by each memory cell in the physical erasing units of the second area is less than the number of data bits stored by each memory cell in the physical erasing units of the first area,

wherein the memory control circuit unit is further configured to receive first data,

wherein the memory control circuit unit writes the first data into one physical erasing unit among the physical erasing units of the first area without taking a pathway via the second area if the number of a physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is less than a predetermined value,

wherein the memory control circuit unit is further configured to write the first data into at least one physical erasing unit among the physical erasing units of the second area if the number of the physical erasing unit having only part of physical programming units being programmed among the physical erasing units of the first area is not less than the predetermined value.