Nonvolatile memory system with background reference positioning and local reference positioning

• US 10,283,215 B2
• Filed: 07/20/2017
• Issued: 05/07/2019
• Est. Priority Date: 07/28/2016
• Status: Active Grant

• Current Assignee: Ip Gem Group, LLC
• Original Assignee: Ip Gem Group, LLC
• Inventors: Marelli, Alessia, Micheloni, Rino, Cohen, Ron, Mosek, Amir, Kirzner, Eran
• Primary Examiner(s): Nguyen, Steve N
• Application Number:
  US15/655,518
• Publication Number:
  US 20180033490A1
• Time in Patent Office: 656 Days
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/1202 Word line control
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/12005 comprising voltage or current generators
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/46 Test trigger logic
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/50016 of retention
• CPC Class Codes: G11C 29/52 : Protection of memory contents; Detection of errors in memory contents

Abstract

A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory system includes a read circuit that performs background reads of an indicator page of each block to identify outlier blocks. A background reference positioning circuit performs background reads of representative pages of the outlier block at threshold voltage offsets to identify sets of updated threshold voltage offset values. Upon endurance events, retention timer events and read disturb events at a closed block background reads are performed of representative pages of the closed block at threshold voltage offsets to identify sets of updated threshold voltage offset values. When a usage characteristic meets one or more usage characteristic threshold, the read circuit performs subsequent host-requested reads of pages of blocks meeting the usage characteristic threshold using a threshold voltage shift read instruction and using the corresponding set of updated threshold voltage offset values.

Claims

1. A method for reducing latency of a nonvolatile memory controller comprising:

identifying a plurality of page groups in each block of a nonvolatile memory device;

performing a background read of an indicator page of each block of the nonvolatile memory device at a predetermined timing interval;

determining the number of errors in the background read of the indicator page of each block;

identifying a block having a determined number of errors exceeding an error threshold as an outlier block;

performing background reads of representative pages of each page group of the outlier block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the outlier block to identify a set of updated threshold voltage offset values for each page group of the outlier block;

upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block, performing background reads of representative pages of each page group of the closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block; and

when a usage characteristic is determined to meet one or more usage characteristic threshold, performing subsequent host-requested reads of pages of each block meeting the one or more usage characteristic threshold using a threshold voltage shift read instruction and using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

2. The method of claim 1 wherein a first usage characteristic is the number of errors in the background read of the indicator page and wherein a first usage characteristic threshold is the error threshold, and wherein the usage characteristic is determined to meet the one or more usage characteristic threshold when the number of errors in any background read of an indicator page of the block exceeds the error threshold.

3. The nonvolatile memory controller of claim 2 further comprising a second usage characteristic that comprises a number of program and erase cycles and a second usage characteristic threshold that is a program and erase cycle threshold, and wherein the usage characteristic is determined to meet the one or more usage characteristic threshold when the number of program and erase cycles of the block exceeds the number of program and erase cycles of the program and erase cycle threshold.

4. The method of claim 1 further comprising:

storing a local reference positioning table that includes a plurality of local reference positioning correction values;

determining the order in which the plurality of local reference positioning correction values are to be applied to decode failures by determining whether the current number of program and erase cycles for the page being read is near the next endurance threshold, determining whether the current read count for the page being read is near the next read disturb threshold and whether the current retention time is near the next retention time threshold;

based on the determined order, adding a first one of the local reference positioning correction values to each of the threshold voltages in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a first set of local reference positioning threshold voltage offset values;

based on the determined order, adding a second one of the local reference positioning correction values to each of the threshold voltages in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a second set of local reference positioning threshold voltage offset values;

based on the determined order, adding a third one of the local reference positioning correction values to each of the threshold voltages in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a third set of local reference positioning threshold voltage offset values;

upon a first decode failure of a read of the page being read reading the failed page using the first set of local reference positioning threshold voltage offset values;

upon a second decode failure of a read of the page being read reading the failed page using the second set of local reference positioning threshold voltage offset values; and

upon a third decode failure of a read of the page being read reading the failed page using the third set of local reference positioning threshold voltage offset values.

5. The method of claim 4 wherein the method further comprises:

summing the errors from each read at an offset to a threshold voltage;

determining the error sum having the least number of errors; and

identifying the set of updated threshold voltage offset values to include the threshold voltage offset value corresponding to the error sum determined to have the least number of errors.

6. A nonvolatile memory controller comprising:

a status circuit configured to determine a usage characteristic of a nonvolatile memory device that includes a plurality of blocks, each block including a plurality of page groups; and

a read circuit coupled to the status circuit and configured to perform a background read of an indicator page of each block of the nonvolatile memory device at a predetermined timing interval to identify outlier blocks, wherein a block is identified as outlier block when the number of errors in the background read of an indicator page of the block exceeds an error threshold;

a background reference positioning circuit coupled to the read circuit, the background reference positioning circuit configured to perform background reads of representative pages of each page group of the outlier block at offsets to each threshold voltage that is required for reading the representative pages of the outlier block to identify a set of updated threshold voltage offset values for each page group of the outlier block, and upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block the read circuit is further configured to perform background reads of representative pages of each page group of the closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block; and

wherein the read circuit is configured to determine whether a usage characteristic meets one or more usage characteristic threshold and, when the usage characteristic is determined to meet the one or more usage characteristic threshold, the read circuit is configured to perform subsequent host-requested reads of pages of each block meeting the one or more usage characteristic threshold using a threshold voltage shift read instruction and using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

7. The nonvolatile memory controller of claim 6 wherein a first usage characteristic of the one or more usage characteristics is the number of errors in the background read of the indicator page and wherein a first usage characteristic threshold is the error threshold, and wherein the one or more usage characteristic is determined to meet the one or more usage characteristic threshold when the number of errors in any background read of an indicator page of the block exceeds the error threshold.

8. The nonvolatile memory controller of claim 7 further comprising a second usage characteristic that comprises a number of program and erase cycles and a second usage characteristic threshold that is a program and erase cycle threshold, and wherein the usage characteristic is determined to meet the one or more usage characteristic threshold when the number of program and erase cycles of the block exceeds the number of program and erase cycles of the program and erase cycle threshold.

9. The nonvolatile memory controller of claim 8 wherein the local reference positioning correction values include an endurance correction value, a retention timing correction value and a read disturb correction value, and wherein the local reference positioning circuit is operable to add one of the local reference positioning correction values to each of the threshold voltages in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain the first set of local reference positioning threshold voltage offset values and further wherein the local reference positioning circuit is operable to add a different one of the endurance correction value, the retention timing correction value and the read disturb correction value to each of the offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a second set of local reference positioning threshold voltage offset values, and further wherein the read circuit is operable upon a second decode failure to read the failed page using the second set of local reference positioning offset values.

10. The nonvolatile memory controller of claim 6 further comprising memory storage configured to store a background reference positioning table that includes each of the identified sets of updated threshold voltage offset values and corresponding index values and wherein the read circuit is configured to identify threshold voltage offset values to be used in the subsequent host-requested reads by indexing the background reference positioning table using an index value corresponding to the page group of the page being read.

11. The nonvolatile memory controller of claim 6 wherein the memory storage is further configured to store a plurality of local reference positioning correction values, the nonvolatile memory controller further comprising:

a local reference positioning circuit coupled to the read circuit and operable to add one of the local reference positioning correction values to each of the threshold voltage offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a first set of local reference positioning offset values; and

wherein the read circuit is operable upon a first decode failure to read the failed page using the first set of local reference positioning offset values.

12. The nonvolatile memory controller of claim 6 wherein blocks of the nonvolatile memory device are grouped into a plurality of block groups and wherein pages within each block group are grouped into a plurality of page groups.

13. The nonvolatile memory controller of claim 12 wherein the status circuit is operable to determine closed block retention time for each closed block of the nonvolatile memory device, and wherein the background reference positioning circuit is configured to determine that a retention timer event has occurred each time that the closed block retention time reaches a threshold retention time.

14. The nonvolatile memory controller of claim 13 wherein the status circuit is operable to determine a number of reads for each block of the nonvolatile memory device and wherein the background reference positioning circuit is configured to determine that a read disturb event has occurred each time that the number of reads for the closed block reaches a threshold number of reads.

15. The nonvolatile memory controller of claim 6 wherein the read circuit is operable to assign priority values to read instructions and is operable to perform the background reads by assigning a lower priority to background read instructions than the priority assigned to read instructions generated in response to read requests from a host computing device.

16. A nonvolatile memory system comprising:

a plurality of nonvolatile memory devices that each include a plurality of blocks, each block including a plurality of page groups;

a memory controller coupled to each of the nonvolatile memory devices, the memory controller configured to perform program operations and read operations on memory cells of the nonvolatile memory devices, the nonvolatile memory controller comprising;

a status circuit configured to determine a usage characteristic of a nonvolatile memory device; and

a read circuit coupled to the status circuit and configured to perform a background read of an indicator page of each block of the nonvolatile memory device at a predetermined timing interval to identify outlier blocks, wherein a block is identified as outlier block when the number of errors in the background read of the indicator page exceeds an error threshold;

a background reference positioning circuit coupled to the read circuit, the background reference positioning circuit configured to perform background reads of representative pages of each page group of the outlier block at offsets to each threshold voltage that is required for reading the representative pages of the outlier block to identify a set of updated threshold voltage offset values for the outlier block, and upon the occurrence of one or more of an endurance event, a retention timer event and a read disturb event at a closed block the read circuit is further configured to perform background reads of representative pages of each page group of the closed block at offsets to each threshold voltage that is required for reading the representative pages of each page group of the closed block to identify a set of updated threshold voltage offset values for each page group of the closed block; and

wherein the read circuit is configured to determine whether a usage characteristic meets one or more usage characteristic threshold and, when the usage characteristic is determined to meet the one or more usage characteristic threshold, the read circuit is configured to perform subsequent host-requested reads of pages of each block meeting the one or more usage characteristic threshold using a threshold voltage shift read instruction and using the set of updated threshold voltage offset values corresponding to the page group of the page being read.

17. The nonvolatile memory system of claim 16 wherein a first usage characteristic is the number of errors in the background read of the indicator page and wherein a first usage characteristic threshold is the error threshold, and wherein the usage characteristic is determined to meet one or more usage characteristic threshold when the number of errors in any background read of a representative page of a block exceeds the error threshold.

18. The nonvolatile memory system of claim 17 further comprising memory storage configured to store a background reference positioning table that includes each of the identified sets of updated threshold voltage offset values and corresponding index values and wherein the read circuit is configured to identify threshold voltage offset values to be used in the subsequent host-requested reads by indexing the background reference positioning table using an index value corresponding to the page group of the page being read.

19. The nonvolatile memory system of claim 16 further comprising memory storage configured to store a plurality of local reference positioning correction values, the nonvolatile memory controller further comprising:

a local reference positioning circuit coupled to the read circuit and operable to add one of the local reference positioning correction values to each of the threshold voltage offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a first set of local reference positioning offset values; and

wherein the read circuit is operable upon a first decode failure to read the failed page using the first set of local reference positioning offset values.

20. The nonvolatile memory system of claim 19 wherein the local reference positioning correction values include an endurance correction value, a retention timing correction value and a read disturb correction value, and wherein the local reference positioning circuit is operable to add one of the local reference positioning correction values to each of the threshold voltages in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain the first set of local reference positioning threshold voltage offset values and further wherein the local reference positioning circuit is operable to add a different one of the endurance correction value, the retention timing correction value and the read disturb correction value to each of the offset values in the set of updated threshold voltage offset values corresponding to the page group of the page being read to obtain a second set of local reference positioning threshold voltage offset values, and further wherein the read circuit is operable upon a second decode failure to read the failed page using the second set of local reference positioning offset values.