Metal gate structure and methods thereof

• US 10,283,503 B2
• Filed: 10/31/2017
• Issued: 05/07/2019
• Est. Priority Date: 07/31/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Ming-Chi, Chuang, Ying-Liang, Yeh, Ming-Hsi, Huang, Kuo-Bin
• Primary Examiner(s): Enad, Christine A
• Application Number:
  US15/799,555
• Publication Number:
  US 20190035786A1
• Time in Patent Office: 553 Days
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32135 by vapour etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

Claims

1. A method of semiconductor device fabrication, comprising:

forming a first fin and a second fin on a substrate, the first fin having a first gate region and the second fin having a second gate region;

forming a metal-gate line over the first and second gate regions, wherein the metal-gate line extends from the first fin to the second fin; and

performing a line-cut process to separate the metal-gate line into a first gate line and a second gate line, wherein the line-cut process includes;

forming a patterned hard mask over the metal-gate line, wherein the patterned hard mask defines an opening;

after forming the patterned hard mask with an opening, performing a first etch through the opening to remove a first portion of a plurality of metal layers of the metal-gate line;

after the first etch, performing a second etch to remove a second portion of the metal-gate line, the second portion including a region of at least one metal layer of the plurality of metal layers; and

after the second etch, performing a third etch to remove a third portion of the metal-gate line, the third portion including a residual portion of a gate dielectric layer.

2. The method of claim 1, wherein the first etch is a dry etch, the second etch is a dry etch, and the third etch is a wet etch.

3. The method of claim 1, wherein the first etch is an anisotropic etch and the second etch is an isotropic etch.

4. The method of claim 1, wherein the second etch removes a residual portion of the at least one metal layer of the plurality of metal layers of the metal-gate line, the at least one metal layer being disposed directly on the gate dielectric layer.

5. The method of claim 4, wherein the at least one metal layer includes titanium nitride.

6. The method of claim 5, wherein the at least one metal layer further includes silicon.

7. The method of claim 1, wherein the third etch removes the third portion of the metal-gate line that includes a residual portion of a gate dielectric layer.

8. The method of claim 7, wherein the residual portion of the gate dielectric layer is hafnium oxide.

9. A method, comprising:

forming a metal gate structure in a trench over a substrate, wherein the forming the metal gate structure includes;

forming a gate dielectric layer;

forming a first metal layer over the gate dielectric layer; and

forming a second metal layer over the first metal layer; and

performing a cut gate process on the metal gate structure to form a first portion of the metal gate structure and a second portion of the metal gate structure, the first and second portions having a cut region therebetween, wherein the performing the cut gate process includes;

performing a first etching process to remove a first region of the second metal layer, a first region of the first metal layer and a first region of the gate dielectric layer;

performing a second etching process to remove a second region of the first metal layer; and

performing a third etching process to remove a second region of the gate dielectric layer.

10. The method of claim 9, further comprising:

forming a dielectric material in the cut region after the performing the third etching process.

11. The method of claim 9, wherein the second metal layer is completely removed from the cut region by the first etching process.

12. The method of claim 11, wherein the first metal layer is completely removed from the cut region by a combination of the first etching process and the second etching process.

13. The method of claim 12, wherein the gate dielectric layer is completely removed from the cut region by a combination of the first etching process, the second etching process, and the third etching process.

14. The method of claim 9, wherein the second etching process is selective to the first metal layer.

15. The method of claim 9, wherein the third etching process is selective to the gate dielectric layer.

16. A method, comprising:

forming a metal gate structure over a substrate, wherein the metal gate structure includes a gate dielectric layer and a plurality of metal layers; and

performing a cut gate process on the metal gate structure to form a first portion of the metal gate structure and a second portion of the metal gate structure, the first portion and the second portion having a space therebetween, wherein the performing the cut gate process includes;

performing a first etching process to remove a first region of each of the plurality of metal layers;

performing a second etching process to remove a second region of at least one of the plurality of metal layers; and

performing a third etching process to remove a residual region of the gate dielectric layer.

17. The method of claim 16, wherein the performing the first etching process removes a first region of the gate dielectric layer, the first region not including the residual region.

18. The method of claim 16, wherein at least another one of the plurality of metal layers is completely removed from the space by the first etching process.

19. The method of claim 16, wherein the at least one of the plurality of metal layers is completely removed from the space by a combination of the first etching process and the second etching process.

20. The method of claim 16, further comprising:

filling the space with a dielectric material after the third etching process.