Super-saturation current field effect transistor and trans-impedance MOS device

• US 10,283,506 B2
• Filed: 07/29/2016
• Issued: 05/07/2019
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: Circuit Seed, LLC
• Original Assignee: Circuit Seed, LLC
• Inventors: Schober, Susan Marya, Schober, Robert C.
• Primary Examiner(s): Taylor, Earl N
• Application Number:
  US15/748,908
• Publication Number:
  US 20180308843A1
• Time in Patent Office: 1,012 Days
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03F 1/086 with FET's
• CPC Class Codes: H03F 2203/45246 the dif amp being biased in the subthreshold region
• CPC Class Codes: H03F 3/04 with semiconductor devices only
• CPC Class Codes: H03F 3/165 with junction-FET's
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence

Abstract

The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.

Claims

1. A field effect transistor, comprising

a. a semiconductor substrate of a first conductivity type, having

a source terminal, a drain terminal, a diffusion terminal, a first gate terminal, and a second gate terminal;

a source channel is defined between said source terminal and diffusion terminal,

a drain channel is defined between said drain terminal and diffusion terminal;

said first gate terminal is capacitively coupled to said source channel; and

said second gate terminal is capacitively coupled to said drain channel;

wherein the diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel.

2. A composite transistor, comprising:

a. a N-type field effect transistor (NxiFET) and a P-type field effect transistor (PxiFET), each comprising

i. a semiconductor substrate of a corresponding conductivity type, having

a source terminal, a drain terminal, a diffusion terminal, a first gate terminal, and a second gate terminal;

a source channel is defined between said source terminal and diffusion terminal,

a drain channel is defined between said drain terminal and diffusion terminal;

said first gate terminal is capacitively coupled to said source channel; and

said second gate terminal is capacitively coupled to said drain channel;

wherein the diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel;

wherein

said source terminal of said NxiFET receives negative supply voltage;

said source terminal of said PxiFET receives positive supply voltage;

said drain terminal of said NxiFET and said drain terminal of said PxiFET are coupled together to form an output; and

the second gate terminal of said NxiFET and the second gate terminal of said PxiFET are coupled together to form an input.

3. A focal plane array read out, comprising:

a. a P-type current field effect transistor (PiFET) and an N-type current field effect transistor (NxiFET),

i. said PiFET comprising a semiconductor substrate of a corresponding conductivity type, having

a source terminal, a drain terminal, a diffusion terminal, and a gate terminal;

a source channel is defined between said source terminal and said diffusion terminal,

a drain channel is defined between said drain terminal and said diffusion terminal;

said gate terminal is capacitively coupled to said source channel and said drain channel; and

wherein the diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel;

ii. said NxiFET comprising a semiconductor substrate of a corresponding conductivity type, having

a source terminal, a drain terminal, a diffusion terminal, a first gate terminal, and a second gate terminal;

a source channel is defined between said source terminal and diffusion terminal,

a drain channel is defined between said drain terminal and diffusion terminal;

said first gate terminal is capacitively coupled to said source channel; and

said second gate terminal is capacitively coupled to said drain channel;

wherein the diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel;

wherein said drain terminal of said PiFET and said drain terminal of said NxiFET are connected together to form an output;

said source terminal of said PiFET is coupled to a positive power supply;

said source terminal of said NxiFET is coupled to a negative power supply;

said diffusion terminal of said PiFET receives an gain control signal;

said gate terminal of said PiFET receives a bias voltage;

b. a switch operable by a select signal having first and second phases; and

c. a capacitor for storing a pixel voltage from a photodiode, having a first and second terminals, said second terminal of said capacitor is coupled to said negative power supply and said first terminal of said capacitor receives said pixel voltage from said photodiode, and said first terminal is coupled to said second gate terminal of said NxiFET;

wherein, during said first phase of said select signal, said switch causes said bias voltage to couple with said first gate terminal of said NxiFET;

during said second phase of said select signal, said switch causes said negative power supply to couple with said first gate terminal.

4. A latch current comparator, comprising:

a. a differential amplifier for amplifying difference between a first input and a second input, each of said first and second inputs having negative and positive polarity inputs, comprising;

i. a first complementary pair of a first n-type current field-effect transistor (NiFET) and a first p-type current field-effect transistor (PiFET);

ii. a second complementary pair of a second NiFET and a second PiFET; and

iii. a third complementary pair of a third NiFET and a third PiFET; and

b. a comparator, comprising;

i. a fourth complementary pair of a fourth NiFET and a fourth PiFET;

ii. a fifth complementary pair of a fifth NiFET and a fifth PiFET;

iii. a plurality of switches operable on a control signal that alternates enable and setup phases;

iv. a first capacitor and a second capacitor, each has a first terminal and a second terminal;

wherein each of said NiFETs and PiFETs comprises;

a source terminal, a drain terminal, a gate terminal, and a diffusion terminal of said corresponding conductivity type of said each of PiFET and NiFET, defining a source channel between said source terminal and said diffusion terminal, and a drain channel between said drain terminal and said diffusion terminal, said diffusion terminal causes changes in said diffused charge density throughout said source and drain channels, and said gate terminal is capacitively coupled to said source channel and said drain channel;

wherein said gate terminal of said PiFET and said gate terminal of said NiFET are connected together to form a common gate terminal for said each complimentary pair, said source terminal of said NiFET of said each complimentary pair is connected to negative power supply and said source terminal of said PiFET of said each pair is connected to positive power supply, and drain terminals of said NiFET and said PiFET of said each complimentary pair are connected together to form an output; and

wherein said common gate of said first complimentary pair, said common gate of said second complementary pair and said common gate of said third complementary pair are connected with said output of said second complementary pair for generating a bias voltage output;

said diffusion terminal of said third PiFET receives said negative polarity input of said first input;

said diffusion terminal of said first PiFET receives said positive polarity input of said first input;

said diffusion terminal of said third NiFET receives said negative polarity input of said second input;

said diffusion terminal of said first NiFET receives said positive polarity input of said second input; and

said output of said first complementary pair forms positive voltage output of said differential amplifier;

said output of said third complementary pair forms negative voltage output of said differential amplifier;

wherein said output of said fourth complementary pair is capacitively coupled to said input of said fifth complementary pair through said second capacitor;

said second terminal of said first capacitor is coupled to said input of said fourth complementary pair;

during said setup phase of said control signal, said plurality of switches cause said positive voltage output of said differential amplifier to be coupled with said first terminal of said first capacitor, said fourth complementary pair to be self-biased by connecting said output of said fourth complementary pair to said input of said fourth complementary pair, and said fifth complementary pair to be self-biased by connecting said output of said fifth complementary pair to said input of said fifth complementary pair;

during said enable phase of said control signal, said plurality of switches cause said negative voltage output of said differential amplifier to be coupled to said first terminal of said first capacitor, and said output of said fifth complementary pair to said input of said fourth complementary pair.