Via support structure under pad areas for BSI bondability improvement

• US 10,283,549 B2
• Filed: 07/26/2018
• Issued: 05/07/2019
• Est. Priority Date: 12/29/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Sin-Yao, Wang, Ching-Chun, Yaung, Dun-Nian, Hung, Feng-Chi
• Primary Examiner(s): Le, Thao P
• Application Number:
  US16/046,183
• Publication Number:
  US 20180350865A1
• Time in Patent Office: 285 Days
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Some embodiments of the present disclosure relate to a method of forming an integrated chip. The method includes forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate. One or more vias are formed on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer. One or more additional vias are formed within the second ILD layer. Respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias. A thickness of the substrate is reduced, and the substrate is etched to form a bond pad opening extending through the substrate to the first interconnect wire. A bond pad is formed within the bond pad opening and directly over the one or more vias.

Claims

1. A method of forming an integrated chip, comprising:

forming a first interconnect wire within a first inter-level dielectric (ILD) layer over a substrate;

forming one or more vias on the first interconnect wire and within a second ILD layer separated from the substrate by the first ILD layer;

forming one or more additional vias within the second ILD layer, wherein respective ones of the one or more vias have a larger size than respective ones of the one or more additional vias;

reducing a thickness of the substrate;

etching the substrate to form a bond pad opening extending through the substrate to the first interconnect wire; and

forming a bond pad within the bond pad opening and directly over the one or more vias.

2. The method of claim 1, wherein the one or more vias and one or more additional vias have surfaces facing the substrate, which are substantially co-planar.

3. The method of claim 1, wherein the one or more vias respectively have a width having a first size and are separated by a space having a second size that is less than the width.

4. The method of claim 1, wherein the one or more vias have a pattern density that is greater than or equal to approximately 40%.

5. The method of claim 1, wherein the one or more vias extend from directly under the bond pad to laterally outside of the bond pad.

6. The method of claim 1,

wherein the one or more vias comprise a plurality of vias having a substantially same size;

and

wherein the plurality of vias are spaced apart from one another by a substantially equal distance along a first direction and along a second direction perpendicular to the first direction.

7. The method of claim 1,

wherein the substrate comprises a semiconductor substrate;

and

wherein the bond pad opening is defined by sidewalls of the semiconductor substrate.

8. The method of claim 1, wherein forming the one or more vias comprises:

depositing the second ILD layer over the first interconnect wire and the first ILD layer;

selectively etching the second ILD layer to form one or more vias holes; and

depositing a conductive material within the one or more via holes.

9. A method of forming an integrated chip, comprising:

forming a first interconnect wire within a first trench in a first inter-level dielectric (ILD) layer located along a front-side of a substrate;

forming one or more vias contacting a first side of the first interconnect wire;

selectively etching a back-side of the substrate and the first ILD layer to form an opening that is defined by sidewalls of the substrate, sidewalls of the first ILD layer, and a second side of the first interconnect wire opposing the first side; and

forming a bond pad within the opening and directly over the one or more vias.

10. The method of claim 9, wherein forming the one or more vias comprises:

depositing a second ILD layer over the first ILD layer and the first interconnect wire;

selectively etching the second ILD layer to form one or more via holes contacting the first side of the first interconnect wire; and

forming a conductive material within the one or more via holes.

11. The method of claim 9, wherein the one or more vias respectively comprise sidewalls continuously surrounding one or more openings extending through a via.

12. The method of claim 9, further comprising:

forming a second interconnect wire within a second trench in the first ILD layer; and

forming a plurality of vias contacting a first side of the second interconnect wire, wherein respective ones of the one or more vias have a larger width than respective ones of the plurality of vias.

13. The method of claim 9, wherein the substrate comprises a semiconductor substrate.

14. The method of claim 9, further comprising:

forming a passivation layer along the sidewalls of the substrate defining the opening.

15. The method of claim 9, wherein the first interconnect wire comprises copper.

16. A method of forming an integrated chip, comprising:

forming a first interconnect wire and a second interconnect wire within a first inter-level dielectric (ILD) layer over a substrate;

forming a first plurality of vias having a substantially same size over the first interconnect wire;

forming a second plurality of vias over the second interconnect wire, wherein respective ones of the first plurality of vias have a larger size than respective ones of the second plurality of vias;

forming a third interconnect wire over the first plurality of vias; and

forming a bond pad directly over the first plurality of vias, wherein the first plurality of vias are spaced apart from one another by a substantially equal distance along a first direction and along a second direction perpendicular to the first direction.

17. The method of claim 16, wherein the first plurality of vias extend from directly under the bond pad to laterally outside of the bond pad.

18. The method of claim 16, further comprising:

forming the bond pad on the third interconnect wire directly over the first plurality of vias.

19. The method of claim 16, further comprising:

selectively etching the substrate and the first ILD layer to form an opening that is defined by sidewalls of the substrate and the first ILD layer; and

forming the bond pad within the opening.

20. The method of claim 16, wherein the first plurality of vias and the second plurality of vias are concurrently formed.