Resistive memory cell having a compact structure

• US 10,283,563 B2
• Filed: 09/01/2017
• Issued: 05/07/2019
• Est. Priority Date: 06/23/2015
• Status: Active Grant

• Current Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SAS (STMicroelectronics NV)
• Inventors: Boivin, Philippe, Jeannot, Simon
• Primary Examiner(s): Bradley, Stephen M
• Application Number:
  US15/694,463
• Publication Number:
  US 20180012935A1
• Time in Patent Office: 613 Days
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 2213/82 Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/061 Patterning of the switching material
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8836 Complex metal oxides, e.g. perovskites, spinels

Abstract

The disclosure relates to a memory cell formed in a wafer comprising a semiconductor substrate covered with a first insulating layer, the insulating layer being covered with an active layer made of a semiconductor, the memory cell comprising a selection transistor having a control gate and a first conduction terminal connected to a variable-resistance element, the gate being formed on the active layer and having a lateral flank covered with a second insulating layer, the variable-resistance element being formed by a layer of variable-resistance material, deposited on a lateral flank of the active layer in a first trench formed through the active layer along the lateral flank of the gate, a trench conductor being formed in the first trench against a lateral flank of the layer of variable-resistance material.

Claims

1. A memory cell comprising:

a selection transistor having a control gate and a first conduction terminal;

a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes;

a semiconductor substrate,

a first insulating layer covering the semiconductor substrate, and

a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,

a second insulating layer covering the lateral flank of the control gate,

a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, and

a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer, wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank, the lower flank contacting the trench conductor, the memory cell comprising a trench isolation positioned between the trench conductor and the upper flank.

2. The memory cell according to claim 1, in which the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

3. The memory cell according to claim 1, in which the layer of variable-resistance material and the trench conductor contact the first insulating layer.

4. The memory cell according to claim 1, in which the substrate, the active layer and the first insulating layer together form an FDSOI substrate.

5. The memory cell according to claim 1, in which the second insulating layer and the layer of variable-resistance material covers a portion of a top of the control gate.

6. The memory cell according to claim 1, further comprising:

a source line coupled a second conduction terminal of the selection transistor;

a bit line coupled to the trench conductor; and

a word line coupled to the control gate.

7. The memory cell according to claim 1, in which the selection transistor includes a second conduction terminal, the second conduction terminal shared with an adjacent memory cell.

8. A memory, comprising:

a semiconductor substrate;

a first insulating layer covering the semiconductor substrate;

a semiconductor active layer covering the first insulating layer; and

a first memory cell that includes;

a selection transistor having a control gate positioned on the semiconductor active layer and a first conduction terminal positioned in the semiconductor active layer, the control gate having a lateral flank;

a variable-resistance element extending through the semiconductor active layer and contacting the first conduction terminal; and

a second insulating layer positioned between the lateral flank of the control gate, and the variable-resistance element, wherein the variable-resistance element includes;

a layer of variable-resistance material contacting a lateral flank of the semiconductor active layer and the first insulating layer, and

a trench conductor formed against a lateral flank of the layer of variable-resistance material and contact the first insulating layer.

9. The memory of claim 8, wherein the lateral flank of the layer of variable-resistance material includes a lower flank and an upper flank, the lower flank contacting the trench conductor, the first memory cell comprising a trench isolation positioned between the trench conductor and the upper flank.

10. The memory of claim 9, in which the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

11. The memory of claim 8, further comprising

a second memory cell that includes:

a second selection transistor having a control gate and first and second conduction terminals, the first and second conduction terminals of the second selection transistor being positioned in the semiconductor layer;

a third insulating layer on a lateral sidewall of the control gate of the second selection transistor; and

a second variable-resistance element on the third insulating layer and extending through the semiconductor layer, the third insulating layer between the control gate of the second selection transistor and the second variable-resistance element, the trench conductor being in a trench in the semiconductor layer between the first variable-resistance element and the second variable-resistance element.

12. The memory of claim 11, further comprising:

a source line being coupled to the second conduction terminals of the first and second memory cells;

a bit line being coupled to the trench conductor; and

first and second word lines being coupled to the control gates of the first and second memory cells, respectively.

13. A memory cell comprising:

a selection transistor having a control gate and a first conduction terminal;

a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes;

a semiconductor substrate,

a first insulating layer covering the semiconductor substrate, and

a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,

a second insulating layer covering the lateral flank of the control gate,

a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, and

a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer, wherein the layer of variable-resistance material and the trench conductor contact the first insulating layer.

14. The memory cell according to claim 13, in which the substrate, the active layer and the first insulating layer together form an FDSOI substrate.

15. The memory cell according to claim 13, in which the second insulating layer and the layer of variable-resistance material covers a portion of a top of the control gate.

16. The memory cell according to claim 13, further comprising:

a source line coupled a second conduction terminal of the selection transistor;

a bit line coupled to the trench conductor; and

a word line coupled to the control gate.

17. A memory cell comprising:

a selection transistor having a control gate and a first conduction terminal;

a variable-resistance element connected to the first conduction terminal, the selection transistor and variable-resistance element being formed in a wafer that includes;

a semiconductor substrate,

a first insulating layer covering the semiconductor substrate, and

a semiconductor active layer covering the insulating layer, the control gate being formed on the active layer and having a lateral flank,

a second insulating layer covering the lateral flank of the control gate,

a first trench formed through the active layer at a lateral flank of the active layer, along the lateral flank of the gate, and reaching the first insulating layer, wherein the variable-resistance element includes a layer of variable-resistance material positioned in the first trench along the lateral flank of the active layer, and

a trench conductor formed in the first trench and against a lateral flank of the layer of variable-resistance material along the lateral flank of the active layer, wherein the second insulating layer and the layer of variable-resistance material covers a portion of a top of the control gate.

18. The memory cell according to claim 17, in which the layer of variable-resistance material is positioned between, and contacts, the trench isolation and the second insulating layer.

19. The memory cell according to claim 17, in which the substrate, the active layer and the first insulating layer together form an FDSOI substrate.

20. The memory cell according to claim 17, in which the second insulating layer and the layer of variable-resistance material covers a portion of a top of the control gate.

21. The memory cell according to claim 17, further comprising:

a source line coupled a second conduction terminal of the selection transistor;

a bit line coupled to the trench conductor; and

a word line coupled to the control gate.