Microelectronic circuits and integrated circuits including a non-silicon substrate

• US 10,283,582 B2
• Filed: 02/25/2013
• Issued: 05/07/2019
• Est. Priority Date: 02/25/2013
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Stenson, Bernard P., Morrissey, Michael, Lynch, Seamus A.
• Primary Examiner(s): Dinh, Tuan T
• Application Number:
  US13/776,545
• Publication Number:
  US 20140240944A1
• Time in Patent Office: 2,262 Days
• Field of Search: 361760, 361766, 361792-795, 174258-262
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/60 Electrodes

Abstract

A microelectronic circuit having at least one component adjacent a carrier that is not a semiconductor or sapphire. The circuit includes a component bearing stack of one or more layers having one or more passive components, which are adjacent or bonded to the carrier. In certain embodiments, the circuit also includes an etch stop layer of a material having a slower etch rate than silicon and a bond layer bonding the carrier and the component bearing one or more layers.

Claims

1. A microelectronic circuit comprising:

a carrier which is not a semiconductor or sapphire;

a microelectromechanical systems (MEMS) switch comprising a first contact, a second contact, and a cantilever extending from the first contact, the MEMS switch integrated with and adjacent to the carrier;

an etch stop layer comprising material that is slower etching than silicon, wherein the etch stop layer has a first side and second side opposite the first side, wherein the MEMS switch is disposed between the first side of the etch stop layer and the carrier, wherein there is no semiconductor layer on the second side of the etch stop layer, and wherein the MEMS switch and the etch stop layer are integrated with each other; and

a plurality of insulating layers arranged in a stack, the stack having a first side and a second side opposite the first side, the first side being bounded by the etch stop layer and at least a portion of the second side being between the MEMS switch and the etch stop layer,

wherein there is a gap between the cantilever and the second contact in a first state, and wherein the cantilever is in contact with the second contact in a second state to thereby provide an electrical connection between the first contact and the second contact in the second state.

2. A microelectronic circuit as claimed in claim 1, in which the carrier functions as a substrate or as a die for the microelectronic circuit.

3. A microelectronic circuit as claimed in claim 1, further comprising one or more components from a group comprising resistors, inductors, transformers, and capacitors, wherein the one or more components are disposed between the MEMS switch and the etch stop layer.

4. A microelectronic circuit as claimed in claim 1, in which the carrier is formed of glass or quartz.

5. A microelectronic circuit as claimed in claim 1, further comprising a bond layer attached to the carrier, in which the bond layer is a glass frit, a metal-metal bond layer or a region treated so as to form an anodic bond.

6. A microelectronic circuit as claimed in claim 1, in which at least one of the plurality of insulating layers is formed of a semiconductor oxide.

7. A microelectronic circuit as claimed in claim 1, further comprising a metal-metal bond layer attached to the carrier and a plurality of supports, wherein the metal-metal bond layer comprises gold.

8. A microelectronic circuit as claimed in claim 1, wherein the etch stop layer comprises at least one of an oxide or a nitride.

9. A microelectronic circuit as claimed in claim 1, further comprising a metal layer configured to protect the MEMS switch from external electrostatic fields.

10. A microelectronic circuit as claimed in claim 1, wherein at least one of the plurality of insulating layers is formed of a semiconductor nitride.

11. A microelectronic circuit comprising:

a glass substrate;

a microelectromechanical systems (MEMS) switch comprising a first contact, a second contact, and a cantilever extending from the first contact and electrical contacts therein;

an etch stop layer comprising a material having a slower etch rate than silicon, wherein the etch stop layer has a first side and second side opposite the first side, wherein the MEMS switch and the etch stop layer are integrated with each other, and wherein the MEMS switch is disposed between the glass substrate and the first side of the etch stop layer;

a plurality of insulating layers arranged in a stack, the stack having a first side and a second side opposite the first side, the first side being bounded by the etch stop layer and at least a portion of the second side being between the MEMS switch and the etch stop layer; and

a bond layer attached to the glass substrate and disposed between the glass substrate and the etch stop layer,

wherein there is a gap between the cantilever and the second contact in a first state, and wherein the cantilever is in contact with both the first contact and the second contact in a second state.

12. A microelectronic circuit as claimed in claim 11, wherein the bond layer is formed of glass frit.

13. A microelectronic circuit as claimed in claim 11, the bond layer is a metal-metal bond layer comprising a plurality of supports.

14. A microelectronic circuit as claimed in claim 11, wherein there is no semiconductor layer on the second side of the etch stop layer that is opposite the bond layer.

15. A microelectronic circuit as claimed in claim 11, wherein the bond layer is attached to a planar surface of the glass substrate that is farthest from an opposite side of the glass substrate.

16. An integrated circuit comprising:

a non-semiconductor substrate having a first side and a second side, the second side opposing the first side;

a microelectromechanical systems (MEMS) switch comprising a first contact, a second contact, and a cantilever extending from the first contact, wherein the MEMS switch is integrated with and adjacent to the non-semiconductor substrate, and wherein there is a gap between the cantilever and the second contact in a first state, and wherein the cantilever is in contact with both the first contact and the second contact in a second state;

supports around the MEMS switch, the supports being disposed on a plurality of layers, and the plurality of layers including a plurality of insulating layers arranged in a stack, wherein the stack is positioned between the MEMS switch and an etch stop layer; and

a bond layer attached to the first side of the non-semiconductor substrate, and the bond layer also being attached to the supports.

17. A circuit as claimed in claim 16, in which the bond layer is formed of glass frit.

18. A circuit as claimed in claim 16, in which at least one of the plurality of insulating layers is formed of a semiconductor oxide.

19. A circuit as claimed in claim 16, wherein the plurality of layers further comprises third to Nth further layers formed of a semiconductor oxide, a semiconductor nitride or polyamide and having metallic tracks forming interconnects, or resistors, or inductors or plates of capacitors formed therein or thereon.

20. An integrated circuit as claimed in claim 16, wherein the etch stop layer comprises a material having a slower etch rate than silicon, wherein the MEMS switch is disposed between the etch stop layer and the bond layer.

21. An integrated circuit as claimed in claim 16, wherein the bond layer is a metal-metal bond layer comprising a plurality of supports.

22. A circuit as claimed in claim 16, wherein at least one of the plurality of insulating layers is formed of a semiconductor nitride.

23. A circuit as claimed in claim 16, wherein the non-semiconductor substrate comprises a glass substrate.

24. A circuit as claimed in claim 16, further comprising a spacer between the non-semiconductor substrate and the plurality of insulating layers.

25. A circuit as claimed in claim 16, further comprising a metal layer configured to protect the MEMS switch from external electrostatic fields.

26. An integrated circuit as claimed in claim 20, wherein there is no semiconductor layer on a side of the etch stop layer that is opposite to the MEMS switch.