Semiconductor device and manufacturing method thereof

• US 10,283,618 B1
• Filed: 12/11/2017
• Issued: 05/07/2019
• Est. Priority Date: 11/07/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chang, Hao-Hsuan, Chung, Yao-Hsien, Tsai, Fu-Yu
• Primary Examiner(s): Turner, Brian
• Application Number:
  US15/838,243
• Publication Number:
  US 20190140074A1
• Time in Patent Office: 512 Days
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A manufacturing method of a semiconductor device includes the following steps. A first stacked structure and a second stacked structure are formed on a core region and an input/output (I/O) region of a semiconductor substrate respectively. The first stacked structure includes a first patterned oxide layer, a first patterned nitride layer, and a first dummy gate. The second stacked structure includes a second patterned oxide layer, a second patterned nitride layer, and a second dummy gate. The first dummy gate and the second dummy gate are removed for forming a first recess above the core region and a second recess above the I/O region. A first gate structure is formed in the first recess and a second gate structure is formed in the second recess. The first patterned nitride layer is removed before the step of forming the first gate structure in the first recess.

Claims

1. A manufacturing method of a semiconductor device, comprising:

providing a semiconductor substrate comprising a core region and an input/output (I/O) region defined thereon;

forming a first stacked structure on the core region, wherein the first stacked structure comprises;

a first patterned oxide layer;

a first patterned nitride layer formed on the first patterned oxide layer; and

a first dummy gate formed on the first patterned nitride layer;

forming a second stacked structure on the I/O region, wherein the second stacked structure comprises;

a second patterned oxide layer;

a second patterned nitride layer formed on the second patterned oxide layer; and

a second dummy gate formed on the second patterned nitride layer;

removing the first dummy gate and the second dummy gate for forming a first recess above the core region and a second recess above the I/O region;

forming a spacer on a sidewall of the first stacked structure and a sidewall of the second stacked structure before the step of removing the first dummy gate and the second dummy gate, wherein the first recess and the second recess are surrounded by the spacer, an oxidation layer is formed on a surface of the spacer by the step of removing the first dummy gate and the second dummy gate, and the first recess and the second recess are surrounded by the oxidation layer;

forming a first gate structure in the first recess;

forming a second gate structure in the second recess; and

removing the first patterned nitride layer before the step of forming the first gate structure in the first recess.

2. The manufacturing method of the semiconductor device according to claim 1, wherein the first patterned oxide layer and the second patterned oxide layer are formed by the same process patterning an oxide dielectric layer.

3. The manufacturing method of the semiconductor device according to claim 1, wherein the first patterned nitride layer and the second patterned nitride layer are formed by the same process patterning a nitride dielectric layer.

4. The manufacturing method of the semiconductor device according to claim 1, wherein the oxidation layer is formed before the step of removing the first patterned nitride layer.

5. The manufacturing method of the semiconductor device according to claim 1, wherein the first gate structure comprises:

a first high dielectric constant (high-k) dielectric layer; and

a first metal gate formed on the first high-k dielectric layer, wherein the first high-k dielectric layer comprises a U-shaped structure surrounding the first metal gate.

6. The manufacturing method of the semiconductor device according to claim 5, wherein the first patterned oxide layer directly contacts the first high-k dielectric layer.

7. The manufacturing method of the semiconductor device according to claim 1, wherein the second gate structure comprises:

a second high-k dielectric layer; and

a second metal gate formed on the second high-k dielectric layer, wherein the second high-k dielectric layer comprises a U-shaped structure surrounding the second metal gate.

8. The manufacturing method of the semiconductor device according to claim 7, wherein the second nitride layer is located between the second high-k dielectric layer and the second patterned oxide layer.

9. A semiconductor device comprising:

a semiconductor substrate comprising a core region and an input/output (I/O) region defined thereon;

a first gate structure disposed on the core region, wherein the first gate structure comprises;

a first high dielectric constant (high-k) dielectric layer; and

a first metal gate disposed on the first high-k dielectric layer, wherein the first high-k dielectric layer comprises a U-shaped structure surrounding the first metal gate in a cross-sectional view of the semiconductor device;

a second gate structure disposed on the I/O region, wherein the second gate structure comprises;

a second high-k dielectric layer; and

a second metal gate disposed on the second high-k dielectric layer, wherein the second high-k dielectric layer comprises a U-shaped structure surrounding the second metal gate in a cross-sectional view of the semiconductor device;

an oxide dielectric layer party disposed between the first gate structure and the semiconductor substrate and partly disposed between the second gate structure and the semiconductor substrate, wherein the oxide dielectric layer disposed between the first gate structure and the semiconductor substrate directly contacts the first high-k dielectric layer; and

a nitride dielectric layer disposed between the second gate structure and the oxide dielectric layer, wherein the nitride dielectric layer is disposed between the second high-k dielectric layer and the oxide dielectric layer, and the nitride dielectric layer directly contacts the second high-k dielectric layer.

10. The semiconductor device according to claim 9, further comprising:

a spacer disposed on a sidewall of the first gate structure, a sidewall of the second gate structure, a sidewall of the oxide dielectric layer, and a sidewall of the nitride dielectric layer.

11. The semiconductor device according to claim 10, further comprising:

an oxidation layer partly disposed between the spacer and the first gate structure and partly disposed between the spacer and the second gate structure.

12. The semiconductor device according to claim 9, wherein the nitride dielectric layer is thicker than the oxide dielectric layer.