Semiconductor device and manufacturing method thereof

• US 10,283,627 B2
• Filed: 07/10/2014
• Issued: 05/07/2019
• Est. Priority Date: 05/29/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Sasaki, Toshinari, Ohara, Hiroki, Sakata, Junichiro
• Primary Examiner(s): Galvin, III, Joseph M
• Application Number:
  US14/328,060
• Publication Number:
  US 20150011049A1
• Time in Patent Office: 1,762 Days
• Field of Search: 438104, 438158, 438159, 438161, 438786, 438787, 257E21414
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a highly reliable semiconductor device including a thin film transistor having stable electric characteristics. In addition, another object is to manufacture a highly reliable semiconductor device at low cost with high productivity. In a method for manufacturing a semiconductor device including a thin film transistor including an oxide semiconductor layer as a channel formation region, the oxide semiconductor layer is heated under a nitrogen atmosphere to lower its resistance, thereby forming a low-resistance oxide semiconductor layer. Further, resistance of a region of the low-resistance oxide semiconductor layer, which is overlapped with a gate electrode layer, is selectively increased, thereby forming a high-resistance oxide semiconductor layer. Resistance of the oxide semiconductor layer is increased by forming a silicon oxide film in contact with the oxide semiconductor layer by a sputtering method.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer comprising indium and zinc over a substrate;

heating the oxide semiconductor layer at 200°

C. or higher under a nitrogen atmosphere to reduce a resistance of the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer after the heating step; and

forming an insulating film comprising silicon and oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer,

wherein the insulating film is in contact with part of the oxide semiconductor layer.

2. The method according to claim 1, further comprising a step of forming a gate electrode layer over the substrate.

3. The method according to claim 2, further comprising a step of forming a gate insulating layer over the gate electrode layer.

4. The method according to claim 1, wherein the insulating film is a silicon oxide film.

5. The method according to claim 1, wherein the part of the oxide semiconductor layer is etched.

6. The method according to claim 1, wherein a resistance of at least the part of the oxide semiconductor layer is increased.

7. A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer comprising indium and zinc over a substrate;

first heating the oxide semiconductor layer at 200°

C. or higher under a nitrogen atmosphere to reduce a resistance of the oxide semiconductor layer;

forming a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer after the first heating step;

forming an insulating film comprising silicon and oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

second heating the insulating film,

wherein the insulating film is in contact with part of the oxide semiconductor layer.

8. The method according to claim 7, further comprising a step of forming a gate electrode layer over the substrate.

9. The method according to claim 8, further comprising a step of forming a gate insulating layer over the gate electrode layer.

10. The method according to claim 7, wherein the insulating film is a silicon oxide film.

11. The method according to claim 7, wherein the part of the oxide semiconductor layer is etched.

12. The method according to claim 7, wherein the second heating step is performed at 300°

C. or lower.

13. The method according to claim 7, wherein a resistance of at least the part of the oxide semiconductor layer is increased.