Manufacturing semiconductor-based multi-junction photovoltaic devices

• US 10,283,666 B2
• Filed: 08/18/2017
• Issued: 05/07/2019
• Est. Priority Date: 06/22/2012
• Status: Active Grant

• Current Assignee: II-VI Delaware, Inc. (Coherent Corp.)
• Original Assignee: Epiworks Inc. (Coherent Corp.)
• Inventors: Ahmari, David, Lim, Swee, Rai, Shiva, Forbes, David
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US15/680,426
• Publication Number:
  US 20170345962A1
• Time in Patent Office: 627 Days
• Field of Search: None
• CPC Class Codes: H01L 31/0336 in different semiconductor regions, e.g. Cu2X/CdX hetero- junctions, X being an element of Group VI of the Periodic Table
• CPC Class Codes: H01L 31/065 the potential barriers being only of the graded gap type
• CPC Class Codes: H01L 31/0687 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/06875 inverted grown metamorphic [IMM] multiple junction solar cells, e.g. III-V compounds inverted metamorphic multi-junction cells
• CPC Class Codes: H01L 31/072 the potential barriers being only of the PN heterojunction type
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 31/076 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
• CPC Class Codes: H01L 31/1852 comprising a growth substrate not being an AIIIBV compound
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing process and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device. A multi-junction cell may include a back surface field layer, a tunneling junction layer, a first active cell, and a second active cell.

Claims

1. A device comprising:

a silicon substrate;

a first active cell including at least part of the silicon substrate;

a back-surface field layer located above the first active cell;

a second active cell located above the back-surface field layer; and

a tunnel junction comprising a first portion and a second portion, the first portion formed within the silicon substrate, the second portion formed above the silicon substrate, the tunnel junction being located between the first active cell and the back-surface field layer.

2. The device of claim 1, wherein the first active cell comprises silicon.

3. The device of claim 1, wherein the second active cell comprises GaP.

4. The device of claim 1, wherein the second portion of the tunnel junction comprises Al_(x)(Ga_(1-x)As_(1-y-z)N_(y)P_(z).

5. The device according to claim 1,

wherein the back-surface field layer comprises Al_(1-Z2)Ga_Z2As_(1-X2-Y2)P_(X2).

6. A device comprising:

a silicon substrate;

a first active cell including at least part of the silicon substrate;

a second active cell located above the first active cell;

a back-surface field layer located above the second active cell; and

a tunnel junction located between the second active cell and the back-surface field layer.

7. The device of claim 6, wherein the tunnel junction comprises Al_(x)Ga_(1-x)As_(1-y-z)N_(y)P_(z).

8. The device of claim 6, further comprising:

a third active cell located above the back-surface field layer.

9. The device according to claim 6, wherein the back-surface field layer comprises Al_(1-Z2)Ga_Z2As_(1-X2-Y2)N_(Y2)P_(X2).

10. A device comprising:

a silicon substrate;

a first active cell including at least part of the silicon substrate;

a back-surface field layer;

a second active cell located above the back-surface field layer; and

a tunnel junction comprising a first portion and a second portion, the first portion of the tunnel junction is closer to the first active cell than to the back-surface field layer,

wherein the second portion of the tunnel junction is closer to the back-surface field layer than to the first active cell, and

wherein the second portion having a polarity that is different from a polarity of the first portion.

11. The device of claim 10, wherein the first portion is n-type and the second portion is p-type.

12. The device of claim 10, wherein the first portion is p-type and the second portion is n-type.

13. The device of claim 10, wherein the second portion comprises GaP.

14. The device of claim 10, wherein the tunnel junction comprises Al_(x)Ga_(1-x)As_(1-y-z)N_(y)P_(z).

15. The device according to claim 10,

wherein the back-surface field layer comprises Al_(1-Z2)Ga_Z2As_(1-X2-Y2)N_(Y2)P_(X2).

16. A method of fabricating a device, comprising:

providing a silicon substrate;

forming a first active cell in a portion of the silicon substrate;

forming at least a portion of a tunnel junction in a surface of the silicon substrate;

forming a back-surface field layer above the tunnel junction; and

forming a second active cell above the back-surface field layer, the second active cell comprising at least one III-IV semiconductor and layer.

17. The method of claim 16, wherein the tunnel junction comprises Al_(x)Ga_(1-x)As_(1-y-z)N_(y)P_(z).

18. The method according to claim 16, wherein forming the back-surface field layer comprises forming the back-surface field of Al_(1-Z2)Ga_Z2As_(1-X2-Y2)N_(Y2)P_(X2).