Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit

• US 10,283,694 B2
• Filed: 08/17/2017
• Issued: 05/07/2019
• Est. Priority Date: 10/07/2013
• Status: Active Grant

• Current Assignee: SeeQC, Inc.
• Original Assignee: Hypres, Inc.
• Inventors: Yohannes, Daniel, Kirichenko, Alexander F., Vivalda, John, Hunt, Richard
• Primary Examiner(s): Armand, Marc Anthony
• Assistant Examiner(s): Brasfield, Quinton A
• Application Number:
  US15/679,935
• Publication Number:
  US 20170345990A1
• Time in Patent Office: 628 Days
• CPC Class Codes: G11C 11/44 using super-conductive elements, e.g. cryotron
• CPC Class Codes: H10N 60/0156 of devices comprising Nb or an alloy of Nb with one or more of the elements of group IVB, e.g. titanium, zirconium or hafnium
• CPC Class Codes: H10N 60/0912 of Josephson-effect devices
• CPC Class Codes: H10N 60/12 Josephson-effect devices
• CPC Class Codes: H10N 60/805 for Josephson-effect devices
• CPC Class Codes: H10N 69/00 Integrated devices, or assemblies of multiple devices, comprising at least one superconducting element covered by group H10N60/00

Abstract

A method for increasing the integration level of superconducting electronic circuits, comprising fabricating a series of planarized electrically conductive layers patterned into wiring, separated by planarized insulating layers, with vias communicating between the conductive layers. Contrary to the standard sequence of patterning from the bottom up, the pattern of vias in at least one insulating layer is formed prior to the pattern of wiring in the underlying conductive layer. This enables a reduction in the number of planarization steps, leading to a fabrication process which is faster and more reliable. In a preferred embodiment, the superconductor is niobium and the insulator is silicon dioxide. This method can provide 10 or more wiring layers in a complex integrated circuit, and is compatible with non-planarized circuits placed above the planarized wiring layers.

Claims

1. A method of forming a planarized integrated circuit on a substrate, comprising a series of successive planarized layers, comprising:

defining a first layer, comprising a first electrically conductive layer, and a second electrically conductive layer on the first electrically conductive layer, by;

patterning the second electrically conductive layer into a first set of solid vias extending vertically above the first electrically conductive layer, and the first electrically conductive layer into a first set of wires;

depositing a first dielectric over the patterned the first set of solid vias and the first set of wires;

etching the deposited first dielectric to produce first Caldera edges over tops of the first set of solid vias as well as dummy patterns over other regions, to create a raised pattern of edges, to permit chemical mechanical polishing in a manner controlled independent of a pattern of the first set of solid vias; and

planarizing the first Caldera edges and the dummy patterns using chemical mechanical polishing to expose the tops of the first set of solid vias surrounded by the first dielectric;

defining a second layer, comprising a third electrically conductive layer, and a fourth electrically conductive layer on the third electrically conductive layer, by;

patterning the fourth electrically conductive layer into a second set of solid vias extending vertically above the third electrically conductive layer, and the third electrically conductive layer into a second set of wires, wherein at least a portion of the second set of solid vias are stacked over a portion of the first set of solid vias to provide a vertically conductive pathway having uniform solid via sizes in the first layer and the second layer;

depositing a second dielectric over the patterned the second set of solid vias and the second set of wires;

etching the deposited second dielectric to produce at least second Caldera edges over tops of the second set of solid vias; and

planarizing the second Caldera edges to expose the tops of the set of solid vias surrounded by dielectric.

2. The method according to claim 1, further comprising depositing an etch stop layer between the first electrically conductive layer and second electrically conductive layer.

3. The method according to claim 2, wherein the second electrically conductive layer is patterned into the first set of solid vias before the first electrically conductive layer is patterned into the first set of wires.

4. The method according to claim 1, wherein the first electrically conductive layer and second electrically conductive layer are in direct contact.

5. The method according to claim 4, wherein the first electrically conductive layer is patterned into the first set of wires before the second electrically conductive layer is deposited.

6. A method of forming a planarized integrated circuit on a substrate, comprising:

providing a stack of at least two planarized layers, formed successively on the substrate, each respective layer comprising;

a first electrically conductive layer, patterned into a set of solid via plugs which define a set of solid vertically extending structures which electrically interconnect with conductive structures of an adjacent overlying layer;

a second electrically conductive layer, patterned into a set of wires by removal of portions of the electrically conductive layer surrounding the set of wires, with the set of solid vertically extending structures extending above the set of wires,

wherein at least a portion of the set of wires of one layer is in electrical contact with a portion of the set of solid via plugs of a preceding layer, and having a portion of the set of solid via plugs of the one layer overlying a portion of the set of solid via plugs of the preceding layer;

depositing a dielectric layer over the set of solid via plugs and the set of wires;

patterning the dielectric layer by an anisotropic etch process etching, to provide a nonplanar raised Caldera pattern surrounding edges of the set of via plugs and a dummy pattern of raised edges over other regions;

chemical mechanical polishing the nonplanar raised Caldera pattern surrounding edges of the set of via plugs and the dummy pattern of raised edges over other regions to planarize the respective layer, with upper surfaces of the set of solid via plugs exposed, wherein the nonplanar raised Caldera pattern surrounding edges of the set of via plugs and the dummy pattern of raised edges over other regions permit the chemical mechanical polishing to proceed in a manner controlled independent of a pattern of the set of solid via plugs.

7. The method according to claim 6, wherein the raised Caldera pattern is formed by a complementary-to-the-metal-mask pattern mask biased for misalignment compensation, and reactive ion etching.

8. The method according to claim 6, wherein the first electrically conductive layer and the second first electrically conductive layer each comprise a niobium-based superconductive material.

9. The method according to claim 6, wherein the dielectric layer comprises silicon dioxide.

10. The method according to claim 6, further comprising at least one non-planarized layer lying above the stack of the at least two planarized layers.

11. The method according to claim 6, further comprising at least one Josephson junction formed within a respective planarized layer, electrically connected to the set of wires, configured as part of a single-flux-quantum circuit.

12. The method according to claim 6, wherein a minimum transverse dimension of the set of wires is less than 1 micron.

13. The method according to claim 6, wherein stack of at least two planarized layers comprises a stack of at least ten planarized layers.

14. The method according to claim 6, wherein the at least one electrically conductive layer is formed by plasma-enhanced, chemical vapor deposition.

15. The method according to claim 6, wherein at least one electrically conductive layer is formed by sputtering.

16. The method according to claim 6, wherein at least one electrically conductive layer is patterned by reactive ion etching.

17. A method of forming a planarized integrated circuit on a substrate, comprising a series of successive planarized layers, comprising:

forming an electrically conductive wiring layer;

forming an electrically conductive via layer;

patterning the electrically conductive via layer into a set of solid vias;

after patterning the electrically conductive via layer, patterning the electrically conductive wiring layer into a set of wires,

wherein portions where the set of solid vias coincide in a plane of the planarized layer with the set of wires define vertically extending conductive solid structures configured to provide a conductive path between the set of wires of the respective layer and a set of wires of an adjacent layer;

forming an insulating layer surrounding the set of wires and the set of vias;

etching the insulating layer to produce first Caldera edges over tops of the set of vias as well as dummy patterns over other regions, to create a raised pattern of edges, to permit chemical mechanical polishing in a manner controlled independent of a pattern of the set of vias; and

planarizing the Caldera edges and the dummy patterns of the insulating layer using chemical mechanical polishing, such that portions of the tops of the vertically extending solid structures are exposed surrounded by the planarized insulating layer substantially dependence on the pattern of the set of vias, and the set of wires is covered.

18. The method to claim 17, further comprising depositing the electrically conductive wiring layer on a planarized surface of a preceding layer, forming an etch stop layer on the electrically conductive wiring layer, and forming the electrically conductive via layer over the etch stop layer, wherein the electrically conductive via layer is initially patterned to expose the etch stop layer surrounding the set of vias, and the portions of the etch stop layer and electrically conductive wiring layer surrounding the set of wires are subsequently removed, such that the set of solid vias comprise the vertically extending solid structures.

19. The method circuit of claim 17, wherein the electrically conductive wiring layer and the electrically conductive via layer are each formed of a cryogenically superconductive material, and the etch stop layer is formed of a material susceptible to induced superconductivity by proximity to the cryogenically superconductive material at cryogenic temperatures.

20. The method of claim 17, wherein the dummy patterns comprise a pattern of narrow peaks extending above a remainder of the insulating layer.