Voltage tolerant termination presence detection

• US 10,284,199 B2
• Filed: 10/02/2017
• Issued: 05/07/2019
• Est. Priority Date: 03/31/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Srivastava, Amit Kumar
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US15/722,985
• Publication Number:
  US 20180123589A1
• Time in Patent Office: 582 Days
• Field of Search: None
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/017509 Interface arrangements

Abstract

Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed.

Claims

1. An apparatus for voltage tolerant termination presence detection, comprising:

detection circuitry coupled to a configuration channel, the detection circuitry to determine whether a device coupled to the configuration channel is to operate in a device mode; and

termination circuitry coupled to the detection circuitry and the configuration channel, wherein the termination circuitry is to set the configuration channel to a logic level low in response to determination that the device is to operate in the device mode.

2. The apparatus of claim 1, wherein the termination circuitry includes pull-down circuitry coupled to the configuration channel, wherein the pull-down circuitry is utilized to set the configuration channel to the logic level low.

3. The apparatus of claim 2, wherein the pull-down circuitry includes one or more resistors coupled to the configuration channel, wherein the one or more resistors are activated to set the configuration channel to the logic level low.

4. The apparatus of claim 3, wherein the pull-down circuitry further includes one or more transistors coupled to the one or more resistors, wherein the one or more transistors control activation of the one or more resistors to set the configuration channel to the logic level low.

5. The apparatus of claim 4, wherein the pull-down circuitry further includes an OR logical construct coupled to each gate of the one or more transistors, wherein the OR logical construct is to receive a signal that indicates the device is to operate in the device mode and cause the one or more transistors to activate the one or more resistors based on the signal.

6. The apparatus of claim 2, wherein the detection circuitry is further to determine whether the device is to operate in a host mode, wherein the pull-down circuitry includes a transistor that disables the pull-down circuitry from setting the configuration channel to the logic level low in response to determination that the device is to operate in the host mode.

7. The apparatus of claim 6, wherein the pull-down circuitry further includes an AND logical construct coupled to a gate of the transistor, wherein the AND logical construct is to receive a signal that indicates that the device is to operate in the host mode and cause the transistor to disable the pull-down circuitry based on the signal.

8. The apparatus of claim 1, further comprising clamping circuitry to limit voltage of the configuration channel to below a maximum voltage.

9. The apparatus of claim 8, wherein the clamping circuitry includes a resistor to sink current from the configuration channel to maintain the voltage of the configuration channel below the maximum voltage.

10. The apparatus of claim 1, wherein the apparatus is located within a system on chip.

11. A system for voltage tolerant termination presence detection, comprising:

a printed circuit board (PCB);

a die mounted to the PCB;

a USB connector mounted to the PCB, the USB connector to couple a device to the die via a configuration channel;

detection circuitry located on the die and coupled to the configuration channel, the detection circuitry to determine whether the device coupled to the configuration channel is to operate in a device mode; and

termination circuitry located on the die and coupled to the detection circuitry and the configuration channel, wherein the termination circuitry is to set the configuration channel to a logic level low in response to determination that the device is to operate in the device mode.

12. The system of claim 11, further comprising clamping circuitry located on the die and coupled to the configuration channel, the clamping circuitry to limit voltage of the configuration channel to below a maximum voltage.

13. The system of claim 12, wherein the clamping circuitry includes a resistor to sink current from the configuration channel to maintain the voltage of the configuration channel below the maximum voltage.

14. The system of claim 11, wherein the termination circuitry includes pull-down circuitry coupled to the configuration channel, wherein the pull-down circuitry is utilized to set the configuration channel to the logic level low.

15. The system of claim 11, wherein the pull-down circuitry includes one or more resistors coupled to the configuration channel, wherein the one or more resistors are activated to set the configuration channel to the logic level low.

16. The system of claim 15, wherein the pull-down circuitry further includes one or more transistors coupled to the one or more resistors, wherein the one or more transistors control activation of the one or more resistors to set the configuration channel to the logic level low.

17. An apparatus for voltage tolerant termination presence detection, comprising:

means for determining whether a device coupled to a configuration channel is to operate in a device mode;

means for setting the configuration channel to a logic level low in response to determination that the device is to operate in the device mode.

18. The apparatus of claim 17, wherein the means for setting the configuration channel includes means for controlling activation of one or more resistors of the means for setting the configuration channel to set the configuration channel to the logic level low.

19. The apparatus of claim 17, further comprising means for limiting voltage of the configuration channel to below a maximum voltage.

20. The apparatus of claim 19, wherein the means for limiting the voltage includes means for causing a resistor of the means for limiting the voltage to sink current from the configuration channel to maintain the voltage of the configuration channel below the maximum voltage.