ECC adjustment based on dynamic error information
First Claim
Patent Images
1. A device comprising:
- a memory;
an error correction code (ECC) decoder configured to perform a first decode operation to decode a first portion of a representation of data read from the memory based on one or more decode parameters and to perform a second decode operation to decode a second portion of the representation of data based on one or more adjusted decode parameters; and
an ECC input adjuster configured to adjust the one or more decode parameters to set the one or more adjusted decode parameters based on a count of bits of the first portion that are erroneous,wherein the count of bits includes at least one of a first count of bits that are erroneous and a second count of bits that are erroneous and that are indicated as reliable.
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Abstract
A device includes a memory, an error correction code (ECC) decoder, and an ECC input adjuster. The ECC decoder is configured to perform a first decode operation to decode a first portion of a representation of data read from the memory based on one or more decode parameters and to perform a second decode operation to decode a second portion of the representation of data based on one or more adjusted decode parameters. The ECC input adjuster is configured to adjust one or more decode parameters to set the one or more adjusted decode parameters based on a count of bits of the first portion that are erroneous.
26 Citations
19 Claims
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1. A device comprising:
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a memory; an error correction code (ECC) decoder configured to perform a first decode operation to decode a first portion of a representation of data read from the memory based on one or more decode parameters and to perform a second decode operation to decode a second portion of the representation of data based on one or more adjusted decode parameters; and an ECC input adjuster configured to adjust the one or more decode parameters to set the one or more adjusted decode parameters based on a count of bits of the first portion that are erroneous, wherein the count of bits includes at least one of a first count of bits that are erroneous and a second count of bits that are erroneous and that are indicated as reliable. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method performed by a controller of a data storage device, the method comprising:
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reading a representation of data from a memory; decoding a first portion of the representation of data; determining a first error count of bits of the first portion that are erroneous and a first bit count of bits of the first portion that are correct and indicated as unreliable; adjusting one or more decode parameters based on the first error count and the firstbit count to set one or more adjusted decode parameters; and decoding a second portion of the representation of data based on the one or more adjusted decode parameters. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A data storage device comprising:
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means for storing data; means for reading a representation of data from the means for storing; means for adjusting first log likelihood ratio (LLR) values based on at least a count of bits of a first portion of the representation of data that are erroneous to set second LLR values; and means for decoding the first portion based on the first LLR values and for decoding a second portion of the representation of data based on the second LLR values, wherein the means for adjusting is configured to adjust the first LLR values based on a first count of bits of the first portion that are erroneous and a second count of bits of the first portion that are erroneous and that are indicated as reliable. - View Dependent Claims (17, 18, 19)
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Specification