Spur cancelation using inverse spur injection

• US 10,284,332 B2
• Filed: 03/03/2017
• Issued: 05/07/2019
• Est. Priority Date: 03/03/2017
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Intel IP Corporation (Intel Corporation)
• Inventors: Avivi, Rotem, Kerner, Michael, Gurevitz, Assaf
• Primary Examiner(s): Chaudry, Mujtaba M
• Application Number:
  US15/449,078
• Publication Number:
  US 20180254852A1
• Time in Patent Office: 795 Days
• Field of Search: None
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/525 with means for reducing leakage of transmitter signal into the receiver
• CPC Class Codes: H04B 7/0404 the mobile station comprising multiple antennas, e.g. to provide uplink diversity
• CPC Class Codes: H04L 1/0033 arrangements specific to the transmitter
• CPC Class Codes: H04L 1/0036 arrangements specific to the receiver
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143

Abstract

A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain. The inverse spur circuitry is configured to, based at least on the error signal, determine a gain and a phase of a spur signal in the transceiver signal and generate an inverse spur signal based at least on the gain and the phase of the spur signal. The injection circuitry is configured to inject the inverse spur signal to cancel a spur in a second transceiver signal in the transceiver signal processing chain.

Claims

1. A spur cancelation system, comprising:

an error circuitry configured to generate an error signal based at least on a first transceiver signal in a transceiver signal processing chain;

an inverse spur circuitry configured to determine a gain and a phase of a spur in the first transceiver signal and generate a digital inverse spur signal based at least on the gain and the phase of the spur signal, the inverse spur circuitry comprising;

a gradient circuitry configured to compute a gradient of a gain of the error signal and a gradient of a phase of the error signal;

a solution circuitry configured to derive an estimated gain coefficient and an estimated phase coefficient based at least on the gradient of the gain and the gradient of the phase; and

an inverse spur generation circuitry configured to generate a digital inverse spur signal based at least on the estimated gain coefficient and the estimated phase coefficient; and

an injection circuitry configured to inject the digital inverse spur signal and cancel a spur in a second transceiver signal in the transceiver signal processing chain.

2. The spur cancelation system of claim 1, wherein the error circuitry comprises filter circuitry configured to filter the first transceiver signal to remove signal components outside a frequency range of an expected spur in the first transceiver signal.

3. The spur cancelation system of claim 1, wherein the first transceiver signal comprises an analog signal and wherein the error circuitry comprises loopback circuitry configured to downconvert the first transceiver signal to a baseband frequency.

4. The spur cancelation system of claim 1, wherein the second transceiver signal comprises an analog receive signal in a receiver signal processing chain, further wherein the injection circuitry comprises a digital to analog converter (DAC) configured to convert the inverse spur signal to an analog signal prior to injecting the inverse spur signal into the analog receive signal.

5. The spur cancelation system of claim 1, wherein the inverse spur generation circuitry comprises a numerically controlled oscillator configured to generate a sinus wave having the gain and the phase of the spur signal.

6. The spur cancelation system of claim 1, wherein:

the first transceiver signal comprises an analog transmit signal in a transmit signal processing chain;

the error circuitry is configured to convert the analog transmit signal to a digital error signal;

the second transceiver signal comprises a digital transmit signal in the transmit signal processing chain.

7. The spur cancelation system of claim 1, wherein:

the first transceiver signal comprises an analog receive signal in a receive signal processing chain;

the error circuitry is configured to convert the analog receive signal to a digital error signal;

the inverse spur circuitry converts the digital inverse spur signal to an analog inverse spur signal; and

the second transceiver signal comprises an analog receive signal in the receive signal processing chain.

8. The spur cancelation system of claim 1, wherein the injection circuitry is configured to combine the inverse spur signal with the second transceiver signal.

9. A method, comprising:

generating an error signal based at least on a first transceiver signal in a transceiver signal processing chain;

based at least on the error signal, determining a gain and a phase of a spur signal in the first transceiver signal and generating a digital inverse spur signal based at least on the gain and the phase of the spur signal by;

computing a gradient of a gain of the error signal and a gradient of a phase of the error signal;

deriving an estimated gain coefficient and an estimated phase coefficient based at least on the gradient of the gain and the gradient of the phase; and

generating a digital inverse spur signal based at least on the estimated gain coefficient and the estimated phase coefficient; and

injecting the digital inverse spur signal into the transceiver signal processing chain.

10. The method of claim 9, further comprising generating the error signal by filtering the first transceiver signal to remove signal components outside a frequency range of the spur signal.

11. The method of claim 9, further comprising generating the error signal by down converting the first transceiver signal to a baseband frequency.

12. The method of claim 9, further comprising converting the inverse spur signal to an analog signal prior to injecting the inverse spur signal into an analog receive signal.

13. A transceiver comprising:

a signal processing chain configured to process a signal;

error circuitry configured to generate an error signal based at least on the signal;

an inverse spur circuitry, comprising;

a gradient circuitry configured to compute a gradient of a gain of the error signal and a gradient of a phase of the error signal;

a solution circuitry configured to derive an estimated gain coefficient and an estimated phase coefficient based at least on the gradient of the gain and the gradient of the phase; and

an inverse spur generation circuitry configured to generate a digital inverse spur signal based at least on the estimated gain coefficient and the estimated phase coefficient; and

an injection circuitry configured to inject the digital inverse spur signal into the signal processing chain to cancel an expected spur from the signal.

14. The transceiver of claim 13, wherein the error circuitry comprises a filter circuitry configured to filter the signal to remove signal components outside a frequency range of the spur.

15. The transceiver of claim 13, wherein the error circuitry comprises loopback circuitry configured to downconvert the signal to a baseband frequency.

16. The transceiver of claim 13, wherein the inverse spur generation circuitry comprises a numerically controlled oscillator configured to generate a sinus wave having the gain and the phase of the spur.

17. The transceiver of claim 13, wherein the solution circuitry is configured to derive the estimated gain coefficient and the estimated phase coefficient using a least mean squares (LMS) algorithm.