Sampler with low input kickback
First Claim
1. An apparatus comprising:
- a differential current generator configured to receive a set of at least three input signals corresponding to symbols of a codeword of a vector signaling code, and to responsively generate, at a pair of output nodes, a differential current representative of combinations of the set of at least three input signals, at least one current of the differential current representing a summation of at least two input signals of the set of at least three input signals;
a sampler connected to the pair of output nodes, the sampler comprising;
a pre-charging field-effect transistor (FET) pair configured to pre-charge the pair of output nodes;
a discharging FET pair configured to receive a sampling clock and to responsively imitate a sampling interval to discharge the pair of output nodes according to the differential current to generate a differential output voltage; and
a latch connected to the pair of output nodes, the latch configured to generate a latched output based on the differential output voltage.
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Abstract
Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.
93 Citations
20 Claims
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1. An apparatus comprising:
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a differential current generator configured to receive a set of at least three input signals corresponding to symbols of a codeword of a vector signaling code, and to responsively generate, at a pair of output nodes, a differential current representative of combinations of the set of at least three input signals, at least one current of the differential current representing a summation of at least two input signals of the set of at least three input signals; a sampler connected to the pair of output nodes, the sampler comprising; a pre-charging field-effect transistor (FET) pair configured to pre-charge the pair of output nodes; a discharging FET pair configured to receive a sampling clock and to responsively imitate a sampling interval to discharge the pair of output nodes according to the differential current to generate a differential output voltage; and a latch connected to the pair of output nodes, the latch configured to generate a latched output based on the differential output voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
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receiving a set of at least three input signals corresponding to symbols of a codeword of a vector signaling code; pre-charging a pair of output nodes using a pre-charging field-effect transistor (FET) pair; generating a pair of currents for discharging the pair of output nodes, the pair of currents generated in response to an initiation of a sampling interval via a sampling clock provided to a discharging FET pair connected to the pair of output nodes, the pair of currents having magnitudes determined by the set of at least three input signals, wherein at least one current of the pair of currents corresponds to a summation of at least two input signals of the set of at least three input signals; and generating a latched output using a latch connected to the pair of output nodes in response to the discharging of the pair of output nodes. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification