Sampler with low input kickback

• US 10,284,362 B2
• Filed: 06/19/2018
• Issued: 05/07/2019
• Est. Priority Date: 04/22/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Ha, Dac V
• Application Number:
  US16/012,646
• Publication Number:
  US 20180302212A1
• Time in Patent Office: 322 Days
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Methods and systems are described for receiving a signal to be sampled and responsively generating, at a pair of common nodes, a differential current representative of the received signal, receiving a plurality of sampling interval signals, each sampling interval signal received at a corresponding sampling phase of a plurality of sampling phases, for each sampling phase, pre-charging a corresponding pair of output nodes using a pre-charging FET pair receiving the sampling interval signal, forming a differential output voltage by discharging the corresponding pair of output nodes via a discharging FET pair connected to the pair of common nodes, the FET pair receiving the sampling interval signal and selectively enabling the differential current to discharge the corresponding pair of output nodes, and latching the differential output voltage.

Claims

1. An apparatus comprising:

a differential current generator configured to receive a set of at least three input signals corresponding to symbols of a codeword of a vector signaling code, and to responsively generate, at a pair of output nodes, a differential current representative of combinations of the set of at least three input signals, at least one current of the differential current representing a summation of at least two input signals of the set of at least three input signals;

a sampler connected to the pair of output nodes, the sampler comprising;

a pre-charging field-effect transistor (FET) pair configured to pre-charge the pair of output nodes;

a discharging FET pair configured to receive a sampling clock and to responsively imitate a sampling interval to discharge the pair of output nodes according to the differential current to generate a differential output voltage; and

a latch connected to the pair of output nodes, the latch configured to generate a latched output based on the differential output voltage.

2. The apparatus of claim 1, wherein the differential current generator comprises a plurality of current sources configured to generate the differential current, each current source receiving a respective input signal of the set of at least three input signals as an input.

3. The apparatus of claim 2, wherein the current representing the summation of the at least two input signals is formed using two or more current sources of the plurality of current sources connected to a corresponding output node via a corresponding discharging FET of the discharging FET pair.

4. The apparatus of claim 2, wherein a magnitude of each current source of the plurality of current source is determined at least in part by a signal level of the respective input signal of the set of at least three input signals.

5. The apparatus of claim 2, wherein each current source of the plurality of current sources is configured to apply a respective weight to the respective input signal of the set of at least three input signals.

6. The apparatus of claim 5, wherein each current source of the plurality of current sources comprises a single transistor configured to apply the weight to the respective input signal of the set of at least three input signals, wherein the weight is determined by a transistor dimension of the single transistor.

7. The apparatus of claim 5, wherein each current source of the plurality of current sources comprises a plurality of equal-dimension transistors connected in parallel, the plurality of equal-dimension transistors each receiving the respective input signal, the plurality of equal-dimension transistors applying the respective weight to the respective input signal of the set of at least three input signals.

8. The apparatus of claim 1, further comprising a differential offset FET pair connected to the pair of output nodes configured to introduce an offset current determined by an offset voltage.

9. The apparatus of claim 1, wherein each input signal of the set of at least three input signals has a signal level selected from a set of at least three possible signal levels.

10. The apparatus of claim 1, wherein the vector signaling code is an orthogonal differential vector signaling code (ODVS).

11. A method comprising:

receiving a set of at least three input signals corresponding to symbols of a codeword of a vector signaling code;

pre-charging a pair of output nodes using a pre-charging field-effect transistor (FET) pair;

generating a pair of currents for discharging the pair of output nodes, the pair of currents generated in response to an initiation of a sampling interval via a sampling clock provided to a discharging FET pair connected to the pair of output nodes, the pair of currents having magnitudes determined by the set of at least three input signals, wherein at least one current of the pair of currents corresponds to a summation of at least two input signals of the set of at least three input signals; and

generating a latched output using a latch connected to the pair of output nodes in response to the discharging of the pair of output nodes.

12. The method of claim 11, wherein the pair of currents are generated using a plurality of current sources, each current source receiving a respective input signal of the set of at least three input signals.

13. The method of claim 12, wherein the current corresponding to the summation of the at least two input signals is formed using two or more current sources of the plurality of current sources connected to a corresponding output node via a corresponding discharging FET of the discharging FET pair.

14. The method of claim 12, wherein a magnitude of each current source of the plurality of current source is determined at least in part by a signal level of the respective input signal of the set of at least three input signals.

15. The method of claim 12, wherein each current source of the plurality of current sources has an associated weighting factor to apply a weight to the respective input signal of the set of at least three input signals.

16. The method of claim 14, wherein the weighting factor of the least one current source corresponds to a transistor dimension of a single transistor.

17. The method of claim 14, wherein the weighting factor of the at least one current source corresponds to a plurality of equal-dimension transistors connected in parallel, the plurality of equal-dimension transistors each receiving the respective input signal.

18. The method of claim 11, further comprising introducing an offset differential current through the pair of output nodes via a differential offset FET pair receiving an offset voltage.

19. The method of claim 11, wherein the discharging of the output nodes forms a differential voltage on the pair of output nodes.

20. The method of claim 11, wherein each input signal of the set of at least three input signals has a signal level selected from a set of at least three possible signal levels.