Method and apparatus to drive layout of arbitrary EM-coil through parametrized cell

• US 10,285,276 B1
• Filed: 09/23/2016
• Issued: 05/07/2019
• Est. Priority Date: 09/23/2016
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Kukal, Taranjit, Ginetti, Arnold, Durrill, Steven R., Agarwal, Abhay, Kohli, Vikas, Lockman, Tyler
• Primary Examiner(s): Tat, Binh C
• Application Number:
  US15/275,230
• Time in Patent Office: 956 Days
• Field of Search: 716118-125, 716136-139
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H05K 3/0005 for designing circuits by computer

Abstract

A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

Claims

1. A method, comprising:

receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout;

transferring the shape data to a schematic cell representation in an EM tool, based on a logic function of the EM structure and a plurality of package technology layers of the circuit layout;

placing, with the EM tool, a symbol for the EM structure in the schematic cell representation;

associating each of the shape data and a model path with a cell parameter in the symbol for the EM structure;

mapping the shape data to the plurality of package technology layers;

specifying a plurality of pins in the schematic cell representation according to the shape data;

verifying a number of ports for the EM structure by associating each pin in the schematic cell representation to a port in the circuit layout;

testing, by providing a test-vector including electric input values for a first port in the EM structure, an EM performance of the EM structure;

determining a figure of merit for the EM performance of the EM structure based on an output value from a second port for the EM structure; and

placing the EM structure in a package layout for fabrication on a printed circuit board according to the package layout.

2. The method of claim 1, wherein receiving shape data comprises receiving shape data for an EM coil, a meander, a taper, or any combination of the above, and the circuit layout corresponds to an electric circuit in a radio-frequency (RF) system.

3. The method of claim 1, wherein receiving shape data comprises retrieving the circuit layout from a graphic database system (GDS) file associated with an electric circuit.

4. The method of claim 1, wherein mapping the shape data from the EM structure to a plurality of package technology layers comprises inspecting the plurality of package technology layers of the circuit layout to detect a presence of a shape.

5. The method of claim 1, wherein specifying a plurality of pins in the schematic cell representation according to the shape data comprises associating a shape in a package technology layer with the plurality of pins in the schematic cell representation.

6. The method of claim 1, wherein mapping the shape data from the EM structure to a plurality of package technology layers of the circuit layout comprises verifying that a number of pins matches a graphic symbol for a shape in at least one of the plurality of package technology layers.

7. The method of claim 1, wherein placing the EM structure in the package layout comprises exporting a compound file to the package layout, the compound file including a GDS file with the circuit layout, a technology layer map, and an electrical model for the EM structure.

8. The method of claim 1, wherein mapping the shape data from the EM structure comprises mapping an irregular shape.

9. The method of claim 1, further comprising verifying an interface consistency between an electrical model of the EM structure, the symbol for the EM structure in the schematic cell representation, and the circuit layout.

10. The method of claim 1, further comprising forming a footprint layout for the EM structure in the package layout using the shape data from the schematic cell representation.

11. The method of claim 1, further comprising simulating a standalone performance of the EM structure in the schematic cell representation and in the package layout.

12. The method of claim 1, further comprising simulating a performance of the EM structure in conjunction with at least another component in the circuit layout.

13. The method of claim 1, further comprising obtaining a selected point in the circuit layout and verifying consistency between the package layout, the schematic cell representation, and an electrical model for the selected point in the circuit layout.

14. The method of claim 1, further comprising overwriting a pin assignment in the EM structure to maintain a pad location in the circuit layout according to a selected shape of the EM structure.

15. The method of claim 1, wherein placing the EM structure in the package layout comprises simulating a performance of the EM structure as one of a standalone component or in combination with at least one other component in the circuit layout.

16. A system, comprising:

a memory, storing computer code; and

at least one processor that executes the computer code to;

receive shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout;

transfer the shape data to a schematic cell representation in an EM tool, based on a logic function of the EM structure and a plurality of package technology layers of the circuit layout;

place, with the EM tool, a symbol for the EM structure in the schematic cell representation;

associate each of the shape data and a model path with a cell parameter in the symbol for the EM structure;

map the shape data to the plurality of package technology layers;

specify a plurality of pins in the schematic cell representation according to the shape data;

verify a number of ports for the EM structure by associating each pin in the schematic cell representation to a port in the circuit layout;

test, by providing a test-vector including electric input values for a first port in the EM structure, an EM performance of the EM structure;

determine a figure of merit for the EM performance of the EM structure based on an output value from a second port for the EM structure; and

place the EM structure in a package layout for fabrication on a printed circuit board according to the package layout, wherein receiving shape data comprises receiving shape data for an EM coil, a meander, a taper, or any combination of the above.

17. The system of claim 16, wherein the at least one processor further executes code to simulate one of a standalone performance of the EM structure in the schematic cell representation or in conjunction with at least another component in the circuit layout.

18. A non-transitory, computer readable medium storing commands which, when executed by a processor cause a computer to perform the steps of:

receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout;

transferring the shape data to a schematic cell representation based on a logic function of the EM structure in an EM tool, and a plurality of package technology layers of the circuit layout;

placing, with the EM tool, a symbol for the EM structure in the schematic cell representation;

associating each of the shape data and a model path with a cell parameter in the symbol for the EM structure;

mapping the shape data to the plurality of package technology layers;

specifying a plurality of pins in the schematic cell representation according to the shape data;

verifying a number of ports for the EM structure by associating each pin in the schematic cell representation to a port in the circuit layout;

testing, by providing a test-vector including electric input values for a first port in the EM structure, an EM performance of the EM structure;

determining a figure of merit for the EM performance of the EM structure based on an output value from a second port for the EM structure; and

placing the EM structure in a package layout for fabrication on a printed circuit board according to the package layout, wherein;

receiving shape data comprises receiving shape data for an EM coil, a meander, a taper, or any combination of the above, and retrieving the circuit layout from a graphic database system (GDS) file associated with an electric circuit.

19. The non-transitory, computer readable medium of claim 18, further storing commands for simulating one of a standalone performance of the EM structure in the schematic cell representation or in conjunction with at least another component in the circuit layout.