Test architecture with a small form factor test board for rapid prototyping

• US 10,288,681 B2
• Filed: 05/17/2018
• Issued: 05/14/2019
• Est. Priority Date: 02/21/2013
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Champoux, Duane, Su, Mei-Mei
• Primary Examiner(s): Dalbo, Michael J
• Application Number:
  US15/982,910
• Publication Number:
  US 20180267101A1
• Time in Patent Office: 362 Days
• CPC Class Codes: G01R 31/2601 Apparatus or methods therefor G01R31/2607, G01R31/2642 take precedence
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/31903 tester configuration
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: G06F 11/263 Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers

Abstract

An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Claims

1. An automated test equipment (ATE) apparatus comprising:

a computer system comprising a system controller, wherein said system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a device under test (DUT) wherein said site module board comprises a compact form factor suitable for use during prototyping, and wherein said site module board is operable to be coupled with said DUT;

the FPGA is communicatively coupled to said tester processor, wherein said FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing said DUT; and

wherein said tester processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said FPGA in a different manner.

2. The apparatus of claim 1 further comprising a memory device coupled to said FPGA and where said memory device stores test pattern data to be written to said DUT.

3. The apparatus of claim 1, wherein dimensions of said site module board are configured to allow said site module board to be used during testing on a desktop of a user.

4. The apparatus of claim 3, wherein said site module board comprises two connectors, wherein a first connector is operable to interface with said system controller and wherein a second connector is operable to interface with a single connected DUT.

5. The apparatus of claim 4, wherein said two connectors are PCIe connectors.

6. The apparatus of claim 1, wherein a test sequence programmed by said system controller on said tester processor and said FPGA is portable to a larger tester comprising multiple tester processors and FPGA components and capable of testing a plurality of DUTs.

7. The apparatus of claim 1 wherein said functional modes comprise four functional modes comprising a bypass mode, said hardware accelerator pattern generator mode, a hardware accelerator memory mode and a hardware accelerator packet builder mode.

8. The apparatus of claim 7 wherein, in the bypass mode, the tester processor is configured to generate all commands and data for coordinating testing of said DUT.

9. The apparatus of claim 7 wherein, in the hardware accelerator pattern generator mode:

said tester processor is configured to generate all commands for coordinating testing of said DUT; and

said hardware accelerator circuit of said FPGA perform a step selected from the group comprising;

generate test pattern data, write said test pattern data to said DUT and compare the data read from said DUT.

10. The apparatus of claim 7 wherein, in the hardware accelerator memory mode:

said tester processor is configured to generate all commands for coordinating testing of said DUT; and

said hardware accelerator circuit of said FPGA performs a step selected from the group comprising;

read said test pattern data from said memory device, write said test pattern data to said DUT and compare the data read from said DUT.

11. The apparatus of claim 7 wherein, in the hardware accelerator packet builder mode, the hardware accelerator circuit of said FPGA is configured to generate both test data and command data for coordinating testing of said DUT.

12. The apparatus of claim 1, wherein said FPGA comprises an IP core, wherein said IP core is operable to be programmed to emulate a protocol, wherein said protocol is selected from a group consisting of:

PCIe, SATA, SAS, or USB.

13. The apparatus of claim 12, wherein said IP core is operable to be re-programmed to emulate a different protocol.

14. A method for testing using an automated test equipment (ATE) comprising:

transmitting instructions from a system controller of a computer system to a tester processor, wherein said system controller is communicatively coupled to a site module board comprising the tester processor and an FPGA, wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of one or two DUTs;

generating commands and data transparently from said tester processor for testing of a plurality of DUTs using a hardware accelerator circuit programmed within an FPGA, wherein said FPGA is communicatively coupled to said tester processor via a bus on said site module board and wherein said hardware accelerator circuit is operable to test said one or two DUTs; and

operating the tester processor in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said FPGA in a different manner.

15. The method of claim 14 further comprising storing test pattern data to be written to said one or two DUTs to a memory device, wherein said memory device is coupled to said FPGA.

16. The method of claim 14 wherein said functional modes comprise four functional modes comprising a bypass mode, the hardware accelerator pattern generator mode, a hardware accelerator memory mode and a hardware accelerator packet builder mode.

17. The method of claim 16 wherein the bypass mode further comprises generating all commands and data for coordinating testing of said one or two DUTs using said tester processor.

18. The method of claim 16 wherein the hardware accelerator pattern generator mode comprises:

generating all commands for coordinating testing of said one or two DUTs using said tester processor; and

using said hardware accelerator circuit to perform a step selected from the group comprising;

generating all test pattern data, writing said test pattern data and comparing the test pattern data read from said one or two DUTs.

19. The method of claim 16, wherein, the hardware accelerator memory mode comprises:

generating all commands for coordinating testing of said one or two DUTs using said tester processor; and

using said hardware accelerator circuit to perform a step selected from the group comprising;

reading test pattern data from said memory device, writing said test pattern data to said one or two DUTs, and comparing the data read from said one or two DUTs.

20. The method of claim 16, wherein the hardware accelerator packet builder mode comprises generating all commands and data for coordinating testing of said one or two DUTs using said hardware accelerator circuit.

21. The method of claim 14, wherein dimensions of said site module board are configured to allow said site module board to be used during testing on a desktop of a user.

22. The method of claim 21, wherein a test sequence programmed by said system controller on said tester processor and said FPGA is portable to a larger tester comprising multiple tester processors and FPGA components and capable of testing a plurality of DUTs.

23. The apparatus of claim 21, wherein said site module board comprises two connectors, wherein a first connector is operable to interface with said system controller and wherein a second connector is operable to interface with a single connected DUT.

24. A tester comprising:

a system controller for controlling a test program for testing one or two DUTs;

a site module board operable to interface with and test said one or two DUTs, said site module board coupled to said system controller, wherein said site module board comprises;

a tester processor coupled to communicate with said system controller to receive instructions and data therefrom in accordance with said test program;

a programmable instantiated tester block coupled to said tester processor via a bus on said site module board, wherein said programmable instantiated tester block is operable to generate test data for application to said one or two DUTs in a way transparent to said test processor, further operable to receive and compare test data generated by said one or two DUTs in a way transparent to said tester processor, and further yet operable to be programmed to communicate with said one or two DUTs in a communication protocol compatible with said one or two DUTs; and

a local memory coupled to said programmable instantiated tester block for storing test data therein; and

one or two connectors for coupling said one or two DUTs to said site module board;

wherein each programmable instantiated tester block is operable in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said programmable instantiated tester block in a different manner.

25. The tester of claim 24, wherein said programmable instantiated tester block is implemented within a Field Programmable Gate Array (FPGA) device.

26. The tester of claim 24, wherein a test sequence programmed by said system controller on said tester processor and said programmable instantiated tester block is portable to a larger tester comprising multiple tester processors and FPGA components and capable of testing a plurality of DUTs.

27. The apparatus of claim 24, wherein said site module board comprises two connectors, wherein a first connector is operable to interface with said system controller and wherein a second connector is operable to interface with a single connected DUT.