Operating parameter offsets in solid state memory devices

• US 10,289,341 B2
• Filed: 06/30/2017
• Issued: 05/14/2019
• Est. Priority Date: 06/30/2017
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Kirshenbaum, Roi, Inbar, Karin, Goldenberg, Idan, Yang, Nian Niles, Rom, Rami, Bazarsky, Alexander, Navon, Ariel, Reusswig, Philip David
• Primary Examiner(s): Rossiter, Sean D
• Application Number:
  US15/640,356
• Publication Number:
  US 20190004734A1
• Time in Patent Office: 683 Days
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06N 3/02 Neural networks
• CPC Class Codes: G06N 3/08 Learning methods
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

Systems and methods are described for generating location-based read voltage offsets in a data storage device. Optimal read voltage thresholds vary across memory elements of a device. However, data storage devices are often limited in the number of read voltage thresholds that can be maintained in the device. Thus, it may not be possible to maintain optimal read voltage parameters for each memory element within a device. The systems and methods described herein provide for increased accuracy of read voltage thresholds when applied to memory elements within a specific location in a device, by enabling the use of location-based read voltage offsets, depending on a relative location of the memory element being read from. The read voltage offsets can be determined based on application of a neural network to data regarding optimal read voltage thresholds determined from at least a sample of memory elements in a device.

Claims

1. A memory device comprising:

a non-volatile memory comprising data blocks, each data block including multiple wordlines, each wordline including at least one non-volatile solid-state memory cell;

a configuration data store storing a plurality read voltage threshold sets, each read voltage threshold set indicating at least a voltage threshold used to read NAND cells associated with the read voltage threshold set; and

a controller comprising a processor and configured to;

generate an input data layer for a neural network algorithm, the input data layer indicating, for each wordline of a plurality of wordlines within the non-volatile memory, a relative location of the wordline within a data block including the wordline;

generate an output data layer for the neural network algorithm, the output data layer including wordline-level offset data identifying, for each wordline of the plurality of wordlines, a read voltage offset for the wordline, the read voltage offset representing a difference between;

i) a voltage threshold indicated within a read voltage threshold set associated with a data block that includes the wordline; and

ii) a voltage threshold determined by the controller to minimize an error rate when reading data from the wordline; and

apply the neural network algorithm to the input data layer and the output data layer to determine correlation information correlating the relative locations of wordlines within data blocks and the read voltages offsets.

2. The memory device of claim 1, wherein the controller is further configured to:

receive a request to read data from a first wordline within a first data block of the non-volatile memory;

determine, from the correlation information, a read voltage offset for the first wordline;

apply the read voltage offset to a voltage threshold indicated within a read voltage threshold set associated with the first data block to result in a modified voltage threshold; and

read data from the first wordline according to the modified voltage threshold.

3. The memory device of claim 1, wherein the input data layer further indicates, for each wordline of the plurality of wordlines, the voltage threshold determined by the controller to minimize the error rate when reading data from the wordline.

4. The memory device of claim 1, wherein each read voltage threshold set indicates a plurality of voltage thresholds, each voltage threshold corresponding to a different potential state of a NAND memory cell.

5. The memory device of claim 4, wherein the wordline-level offset data identifies a plurality of read voltage offsets, each of the read voltage offsets corresponding to a voltage threshold of the plurality of voltage thresholds.

6. A method comprising:

obtaining data regarding a plurality of wordlines within one or more flash memory devices, each wordline corresponding to a grouping of memory cells in a non-volatile memory, the data comprising, for each wordline of the plurality of wordlines;

a relative location of the wordline within a data block containing the wordline;

a read voltage offset for the wordline, the read voltage offset representing a difference between i) a voltage threshold indicated within a read voltage threshold set associated with a data block that includes the wordline and ii) a voltage threshold determined to minimize an error rate when reading data from the wordline;

generating, from the data, an input data layer for a neural network algorithm, the input data layer indicating the relative locations within data blocks of respective wordlines within the plurality of wordlines;

generating, from the data, an output data layer indicating the read voltage offsets for respective wordlines in the plurality of wordlines; and

applying the neural network algorithm to the input data layer and the output data layer to determine correlation information correlating the relative locations of wordlines within data blocks and the read voltages offsets.

7. The method of claim 6, wherein the method is implemented by a flash memory device of the one or more flash memory devices.

8. The method of claim 6 further comprising:

receiving a request to read data from a first wordline within a first data block of the non-volatile memory;

determining, from the correlation information, a read voltage offset for the first wordline;

applying the read voltage offset to a voltage threshold indicated within a read voltage threshold set associated with the first data block to result in a modified voltage threshold; and

reading data from the first wordline according to the modified voltage threshold.

9. The method of claim 6, wherein each data block within the one or more flash memory devices includes wordlines in a plurality of relative locations, and wherein the method further comprises determining, from the correlation information, a read voltage offset for wordlines in each relative location of the plurality of relative locations.

10. The method of claim 6, wherein the non-volatile memory corresponds to at least one of single level cell (SLC) memory or multi-level cell (MLC) memory.

11. The method of claim 10, wherein the MLC memory corresponds to at least one of 2-bits per cell MLC or 3-bits per cell MLC.

12. The method of claim 6, wherein the input data layer further indicates, for each wordline of the plurality of wordlines, the voltage threshold determined to minimize the error rate when reading data from the wordline.

13. Non-transitory computer-readable media including computer-executable instructions that, when executed by a processor, cause the processor to:

obtain data regarding a plurality of wordlines within one or more flash memory devices, each wordline corresponding to a grouping of memory cells in a non-volatile memory, the data comprising, for each wordline of the plurality of wordlines;

a relative location of the wordline within a data block containing the wordline; and

a read voltage offset for the wordline, the read voltage offset representing a difference between i) a voltage threshold indicated within a read voltage threshold set associated with a data block that includes the wordline and ii) a voltage threshold determined to minimize an error rate when reading data from the wordline;

generate, from the data, an input data layer for a neural network algorithm, the input data layer indicating the relative locations within data blocks of respective wordlines within the plurality of wordlines;

generate, from the data, an output data layer indicating the read voltage offsets for respective wordlines in the plurality of wordlines; and

apply the neural network algorithm to the input data layer and the output data layer to determine correlation information correlating the relative locations of wordlines within data blocks and the read voltages offsets.

14. The non-transitory, computer-readable media of claim 13, wherein the computer-executable instructions further include instructions that cause the processor to obtain the data regarding the plurality of wordlines by writing to and reading from the plurality of wordlines.

15. The non-transitory, computer-readable media of claim 13, wherein the plurality of wordlines represents less than all wordlines within the one or more flash memory devices.

16. The non-transitory, computer-readable media of claim 13, wherein the computer-executable instructions further include instructions that cause the processor to:

receive a request to read data from a first wordline within a first data block of the non-volatile memory;

determine, from the correlation information, a read voltage offset for the first wordline;

apply the read voltage offset to a voltage threshold indicated within a read voltage threshold set associated with the first data block to result in a modified voltage threshold; and

read data from the first wordline according to the modified voltage threshold.

17. The non-transitory, computer-readable media of claim 13, wherein each data block within the one or more flash memory devices includes wordlines in a plurality of relative locations, and wherein the computer-executable instructions further include instructions that cause the processor to determine, from the correlation information, a read voltage offset for wordlines in each relative location of the plurality of relative locations.

18. The non-transitory, computer-readable media of claim 13, wherein the input data layer further indicates, for each wordline of the plurality of wordlines, the voltage threshold determined to minimize the error rate when reading data from the wordline.

19. A computing system comprising:

a data store including data regarding a plurality of wordlines within one or more flash memory devices, each wordline corresponding to a grouping of memory cells in a non-volatile memory, the data comprising, for each wordline of the plurality of wordlines;

a relative location of the wordline within a data block containing the wordline; and

a read voltage offset for the wordline, the read voltage offset representing a difference between i) a voltage threshold indicated within a read voltage threshold set associated with a data block that includes the wordline and ii) a voltage threshold determined to minimize an error rate when reading data from the wordline; and

a processor configured with computer-executable instructions to;

generate, from the data, an input data layer for a neural network algorithm, the input data layer indicating the relative locations within data blocks of respective wordlines within the plurality of wordlines;

generate, from the data, an output data layer indicating the read voltage offsets for respective wordlines in the plurality of wordlines; and

apply the neural network algorithm to the input data layer and the output data layer to determine correlation information correlating the relative locations of wordlines within data blocks and the read voltages offsets.

20. The computing system of claim 19, wherein the processor and data store are included within a flash memory device.

21. The computing system of claim 19, wherein the processor is further configured to:

receive a request to read data from a first wordline within a first data block of the non-volatile memory;

determine, from the correlation information, a read voltage offset for the first wordline;

apply the read voltage offset to a voltage threshold indicated within a read voltage threshold set associated with the first data block to result in a modified voltage threshold; and

read data from the first wordline according to the modified voltage threshold.

22. The computing system of claim 19, wherein each data block within the one or more flash memory devices includes wordlines in a plurality of relative locations, and wherein the processor is further configured to determine, from the correlation information, a read voltage offset for wordlines in each relative location of the plurality of relative locations.