Instruction set emulation for guest operating systems

• US 10,289,435 B2
• Filed: 09/10/2015
• Issued: 05/14/2019
• Est. Priority Date: 05/16/2011
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Bond, Barry C., Olinsky, Reuben R., Hunt, Galen C.
• Primary Examiner(s): Alhija, Saif A
• Application Number:
  US14/850,557
• Publication Number:
  US 20160026488A1
• Time in Patent Office: 1,342 Days
• Field of Search: 703 26
• CPC Class Codes: G06F 9/4552 Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM
• CPC Class Codes: G06F 9/45545 Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox

Abstract

The described implementations relate to virtual computing techniques. One implementation provides a technique that can include receiving a request to execute an application. The application can include first application instructions from a guest instruction set architecture. The technique can also include loading an emulator and a guest operating system into an execution context with the application. The emulator can translate the first application instructions into second application instructions from a host instruction set architecture. The technique can also include running the application by executing the second application instructions.

Claims

1. A host computing device comprising:

at least one processing device configured to implement a host instruction set architecture (ISA) that is native to the host computing device; and

at least one computer-readable storage medium storing host ISA instructions,

wherein the at least one computer-readable storage medium includes a memory, and

wherein the host ISA instructions, when executed by the at least one processing device, cause the at least one processing device to;

maintain a translation data structure indicating whether guest ISA binaries have been translated into host ISA binaries and loaded into the memory, the translation data structure mapping guest ISA addresses used by a guest operating system or a guest application to reference the guest ISA binaries to host ISA addresses of the host ISA binaries in the memory, the guest ISA binaries being in a guest ISA that is not native to the host computing device;

receive a request from the guest operating system or the guest application to load a particular guest ISA binary into the memory;

check the translation data structure to determine whether a particular host ISA binary corresponding to the particular guest ISA binary has already been loaded into the memory;

in a first instance when the particular host ISA binary corresponding to the particular guest ISA binary has already been loaded into the memory, execute the particular host ISA binary upon request; and

in a second instance when the particular guest ISA binary has already been translated into the particular host ISA binary in the host ISA and the particular host ISA binary is not yet loaded into the memory;

load the particular host ISA binary into the memory;

update the translation data structure with a record indicating that the particular host ISA binary has been translated and is located in the memory at a particular host ISA address, the record having a particular guest ISA address used by the guest operating system or the guest application to reference the particular guest ISA binary; and

execute the particular host ISA binary upon request.

2. The host computing device of claim 1, wherein the host ISA instructions comprise an emulator configured to translate the guest ISA binaries from the guest ISA to the host ISA to obtain the host ISA binaries.

3. The host computing device of claim 2, wherein the emulator comprises a just-in-time compiler configured to:

in a third instance when the particular guest ISA binary is not loaded into the memory and has not already been translated, defer translation of the particular guest ISA binary until a subsequent request to execute the particular guest ISA binary is received.

4. The host computing device of claim 2, the emulator further comprising a precompiler configured to translate an individual guest ISA binary in advance of receiving another request to load the individual guest ISA binary.

5. The host computing device according to claim 2, the particular guest ISA binary being part of the guest application.

6. The host computing device according to claim 5, the particular guest ISA binary comprising a shared library that is linked at runtime.

7. The host computing device according to claim 2, the particular guest ISA binary being part of the guest operating system, the host computing device having a host operating system other than the guest operating system.

8. The host computing device of claim 7, wherein another guest ISA binary is part of the guest application, the another guest ISA binary having a call to an interface provided by the guest operating system.

9. The host computing device of claim 8, wherein the particular guest ISA binary that is part of the guest operating system implements the interface.

10. A method performed by a computing device having a native instruction set architecture (ISA), the method comprising:

maintaining a translation data structure indicating whether guest ISA binaries have been translated into native ISA binaries and loaded into memory, the translation data structure mapping guest locations of the guest ISA binaries to corresponding host locations of the native ISA binaries, wherein the guest ISA binaries are provided in a guest ISA that is different than the native ISA and the guest locations are used by guest code in the guest ISA to reference the guest ISA binaries;

receiving a request from the guest code to execute an individual guest ISA binary;

checking the translation data structure to determine whether an individual native ISA binary corresponding to the individual guest ISA binary has already been loaded into memory; and

in a first instance when the individual native ISA binary has not already been loaded into memory;

interpreting or compiling the individual guest ISA binary to obtain the individual native ISA binary;

loading the individual native ISA binary into memory at an individual host location;

updating the translation data structure with a record mapping an individual quest location of the individual quest ISA binary to the individual host location of the individual native ISA binary in memory; and

executing the individual native ISA binary in response to the request; and

in a second instance when the individual native ISA binary has already been loaded into memory, executing the individual native ISA binary in response to the request.

11. The method of claim 10, further comprising:

compiling the individual guest ISA binary with a just-in-time compiler.

12. The method of claim 10, wherein the native ISA is a reduced instruction set architecture and the guest ISA is a complex instruction set architecture.

13. The method of claim 10, wherein the native ISA is a complex instruction set architecture and the guest ISA is a reduced instruction set architecture.

14. The method of claim 10, wherein the translation data structure comprises a translation data table and the updating comprises:

after interpreting or compiling the individual guest ISA binary, adding a new row to the translation data table, the new row comprising the record mapping the individual guest location of the individual guest ISA binary to the individual host location of the individual native ISA binary.

15. The method of claim 14, wherein the translation data table comprises a column that includes identifiers of the guest ISA binaries.

16. The method of claim 15, wherein individual rows of the translation data table map different guest locations of different guest ISA binaries to different host locations.

17. The method of claim 16, wherein the translation data table includes separate columns identifying the different guest locations and the different host locations.

18. A method performed by a computing device, the method comprising:

receiving multiple requests to execute guest files;

in response to the multiple requests, translating the guest files into native binaries and loading the native binaries into memory;

updating a translation data structure with records indicating that the guest files have been translated, the translation data structure having mappings of guest locations of the guest files to corresponding host locations of the native binaries in memory, the guest locations being used by guest code to reference the guest files;

executing the native binaries;

receiving subsequent requests to execute individual guest files; and

in response to the subsequent requests;

in first instances when the translation data structure includes records indicating that first native binaries for first guest files remain loaded in memory, executing the first native binaries without recompilation and without reloading into memory; and

in second instances when the translation data structure lacks records indicating that second native binaries for second guest files are compiled and loaded in memory and the second native binaries are not compiled and available in storage;

compiling the second guest files to obtain the second native binaries;

loading the second native binaries into memory;

updating the translation data structure with records indicating that the second native binaries have been compiled and loaded into memory; and

executing the second native binaries.

19. The method of claim 18, wherein the guest files are guest binaries in a guest instruction set architecture and the native binaries are in a native instruction set architecture of the computing device.

20. The method of claim 19, wherein the guest files include both guest application files that are part of a guest application and guest operating system files that are part of a guest operating system, the computing device having a host operating system other than the guest operating system.