Method for accessing flash memory module and associated flash memory controller and memory device
First Claim
1. A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the method comprises:
- encoding data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips;
writing the data into the first super block; and
writing the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;
wherein the at least one parity check code is a temporary parity check code, and the method further comprises;
reading the at least one parity check code from the second super block, and generating a final parity check code according to the at least one parity check code; and
writing the final parity check code into the first super block.
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Accused Products
Abstract
A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
55 Citations
24 Claims
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1. A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the method comprises:
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encoding data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; writing the data into the first super block; and writing the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips; wherein the at least one parity check code is a temporary parity check code, and the method further comprises; reading the at least one parity check code from the second super block, and generating a final parity check code according to the at least one parity check code; and writing the final parity check code into the first super block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the flash memory controller comprises:
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a memory, for storing a program code; a microprocessor, for executing the program code to control access of the flash memory module; and a codec; wherein the codec encodes data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; and
the microprocessor writes the data into the first super block, and writes the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;wherein during the data being written into the super block;
the microprocessor reads a portion of the data, which has been written into the first super block, from the first super block; and
the microprocessor reads at least one portion of the parity check code from the second super block, and uses the at least one portion of the parity check code to perform error correction upon the portion of the data when an error occurs and cannot be corrected during reading the portion of the data. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A memory device, comprising:
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a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages; and a flash memory controller, for accessing the flash memory module; wherein when receiving a write request from a host device to write data into the flash memory module, the flash memory controller encodes the data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; and
the flash memory controller writes the data into the first super block, and writes the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;wherein the at least one parity check code is a temporary parity check code, and the flash memory controller reads the at least one parity check code from the second super block, and generates a final parity check code according to the at least one parity check code, and writes the final parity check code into the first super block. - View Dependent Claims (20, 21)
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22. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the flash memory controller comprises:
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a memory, for storing a program code; a microprocessor, for executing the program code to control access of the flash memory module; and a codec; wherein the codec encodes data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; and
the microprocessor writes the data into the first super block, and writes the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;wherein the at least one parity check code is a temporary parity check code, and the microprocessor reads the at least one parity check code from the second super block, and the codec generates a final parity check code according to the at least one parity check code, and the microprocessor writes the final parity check code into the first super block.
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23. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the flash memory controller comprises:
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a memory, for storing a program code; a microprocessor, for executing the program code to control access of the flash memory module; and a codec; wherein the codec encodes data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; and
the microprocessor writes the data into the first super block, and writes the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;wherein the at least one parity check code is a temporary parity check code, and the microprocessor reads the 1st-Nth parity check codes from the second super block, and the codec generates a plurality of final parity check codes according to the 1st-Nth parity check codes, and the microprocessor writes the plurality of final parity check codes into the first super block.
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24. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks which include a plurality of multiple-level cell blocks and a plurality of single-level cell (SLC) blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the flash memory controller comprises:
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a memory, for storing a program code; a microprocessor, for executing the program code to control access of the flash memory module; and a codec; wherein the codec encodes data to generate at least one parity check code, wherein the data is to be written into a first super block of the flash memory chips, and the first super block includes one multiple-level cell block of each flash memory chip among the flash memory chips; and
the microprocessor writes the data into the first super block, and writes the at least one parity check code into a second super block, wherein the second super block includes one SLC block of each flash memory chip among the flash memory chips;wherein after the final parity check code is written into the first super block, the microprocessor erases contents of the second super block or marks the second super block as invalid/ineffective even if the data stored in the first super block is valid/effective.
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Specification