Forming an isolation barrier in an isolator

• US 10,290,532 B2
• Filed: 05/19/2017
• Issued: 05/14/2019
• Est. Priority Date: 05/19/2017
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Blennerhassett, Alan John, Stenson, Bernard Patrick
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US15/600,664
• Publication Number:
  US 20180337084A1
• Time in Patent Office: 725 Days
• CPC Class Codes: H01F 17/00 Fixed inductances of the signal type coils in general H01F5/00; inductors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof and multistep manufacturing processes therefor H01L28/10
• CPC Class Codes: H01F 2027/2809 on stacked layers
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure pre-formed sheets or tapes of dielectric material are applied to the substrate over the first transformer coil or capacitive plate, for example by being rolled onto the substrate using a heated roller. Such a technique results in a thick isolation layer that is formed using a simple process and much more quickly and reliably than conventional spin-coating or deposition techniques.

Claims

1. A method of forming a dielectric insulation layer in an integrated isolator circuit, comprising:

receiving a partially formed integrated isolator circuit structure having a first electrode set formed on a substrate wafer;

applying a pre-formed dielectric sheet or tape over the partially formed integrated isolator circuit structure;

depositing a metallization layer on the pre-formed dielectric sheet or tape; and

patterning the metallization layer deposited on the pre-formed dielectric sheet or tape to form a second electrode set on the pre-formed dielectric sheet or tape.

2. A method according to claim 1, wherein applying the pre-formed dielectric sheet or tape comprises rolling the pre-formed dielectric sheet or tape onto the partially formed integrated isolator circuit structure from one side of the partially formed integrated isolator circuit structure to another.

3. A method according to claim 2, wherein rolling the pre-formed dielectric sheet or tape comprises rolling the pre-formed dielectric sheet or tape with the aid of a roller tool.

4. A method according to claim 1, wherein the pre-formed dielectric sheet or tape is a polymer material.

5. A method according to claim 4, wherein the pre-formed dielectric sheet or tape is a polyimide sheet or tape.

6. A method according to claim 5, wherein the polyimide sheet or tape is between 40 and 80 microns in thickness.

7. A method according to claim 1, wherein applying the pre-formed dielectric sheet or tape comprises applying the pre-formed dielectric sheet or tape onto a surface of the partially formed integrated isolator circuit structure substantially simultaneously across the surface, the application being performed in a vacuum environment sufficient to prevent formation of gas bubbles beneath the pre-formed dielectric sheet or tape as it is applied.

8. A method according to claim 1, wherein the pre-formed dielectric sheet or tape is a dry film resist.

9. A method according to claim 1, wherein the pre-formed dielectric sheet or tape is a laminating sheet, and wherein the method further comprises dicing the substrate wafer into individual integrated isolator circuit structures after the application of the pre-formed dielectric sheet or tape and before the depositing and the patterning of the metallization layer.

10. A method according to claim 1, wherein the integrated isolator circuit is a digital isolator circuit.

11. A method of fabricating an integrated digital isolator circuit, comprising:

forming a first electrode set on an integrated circuit wafer substrate;

rolling a pre-formed sheet or tape of dielectric material having a predetermined thickness to give a predetermined electrical isolation property over the first electrode set;

depositing a metallization layer on the pre-formed sheet or tape of dielectric material; and

patterning the metallization layer deposited on the pre-formed sheet or tape of dielectric material to form a second electrode set on the pre-formed sheet or tape of dielectric material.

12. A method according to claim 11, further comprising forming a first passivation layer over the first electrode set prior to the rolling of the pre-formed sheet or tape, the first passivation layer having vias formed therein electrically contacting at least part of the first electrode set.

13. A method according to claim 12, further comprising forming a second passivation layer over the second electrode set, the second passivation layer having vias formed therein electrically contacting at least part of the second electrode set.

14. A method according to claim 11, wherein the first and second electrode sets comprise respective conducting coil structures forming a transformer.

15. A method according to claim 11, wherein the first and second electrode sets comprise respective conducting capacitor plates.

16. A method according to claim 11, wherein the pre-formed sheet or tape comprises polyimide or dry-film resist.

17. A method of fabricating an integrated digital isolator circuit, comprising:

applying a dielectric sheet or tape having a predetermined thickness over a first electrode formed on a wafer substrate;

depositing a metallization layer on the dielectric sheet or tape; and

patterning the metallization layer deposited on the dielectric sheet or tape to form a second electrode on the dielectric sheet or tape.

18. The method of claim 17, wherein the dielectric sheet or tape has a substantially uniform thickness.

19. The method of claim 17, wherein the applying the dielectric sheet or tape is performed in a vacuum environment that prevents formation of air or gas bubbles beneath the dielectric sheet or tape.

20. The method of claim 17, wherein the dielectric sheet or tape applied over the first electrode is substantially devoid of wrinkles or folds.