Back-to-back stacked dies
First Claim
Patent Images
1. A circuit comprising:
- a first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier, and wherein the first die includes a high side power transistor and a low side power transistor; and
a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die, wherein the second die includes a controller for the high side power transistor and the low side power transistor,wherein the first die includes a metal layer on the backside, andwherein the metal layer is coupled to a filter network.
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Abstract
Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.
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Citations
18 Claims
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1. A circuit comprising:
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a first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier, and wherein the first die includes a high side power transistor and a low side power transistor; and a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die, wherein the second die includes a controller for the high side power transistor and the low side power transistor, wherein the first die includes a metal layer on the backside, and wherein the metal layer is coupled to a filter network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification