Method of manufacturing a package-on-package type semiconductor package

• US 10,290,621 B2
• Filed: 08/22/2017
• Issued: 05/14/2019
• Est. Priority Date: 08/19/2014
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Dong Jin, Kim, Jin Han, Cha, Se Woong, Lee, Ji Hun, Kim, Joon Dong, Ko, Yeong Beom
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US15/683,065
• Publication Number:
  US 20170373051A1
• Time in Patent Office: 630 Days
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

Claims

1. A method of manufacturing a semiconductor package, the method comprising:

attaching an array of package substrates to a carrier, where each package substrate of the array of package substrates has passed testing prior to said attaching the array of package substrates, and each package substrate of the array of package substrates comprises a top side that comprises a die attach region;

for each package substrate of the array of package substrates attaching a respective semiconductor die to the respective die attach region of said each package substrate, where the respective semiconductor die has passed testing prior to said attaching the respective semiconductor die;

for each package substrate of the array of package substrates, forming a respective stacking terminal on the respective top side of said each package substrate and outside of the respective die attach region of said each package substrate;

forming an encapsulating material that covers at least an upper side of each package substrate of the array of package substrates and at least a lateral side of each of the respective semiconductor dies;

for each package substrate of the array of package substrates, forming a respective interposer on an upper side of the encapsulating material and electrically connected to the respective stacking terminal formed on the respective top side of said each package substrate;

removing the array of package substrates, semiconductor dies, and stacking terminals from the carrier; and

attaching a respective interconnection structure to a respective bottom side of each package substrate of the array of package substrates.

2. The method of claim 1, comprising singulating the package substrates from the array of package substrates by cutting the encapsulating material and without cutting the package substrates.

3. The method of claim 1, wherein said forming the respective interposer comprises stacking a respective preformed interposer on the upper side of the encapsulating material and electrically connecting the respective preformed interposer to the respective stacking terminal, wherein the respective preformed interposer is formed before said stacking the respective preformed interposer.

4. The method of claim 1, comprising after said removing the array of package substrates, semiconductor dies, and stacking terminals from the carrier, reusing the carrier.

5. The method of claim 1, comprising thinning the encapsulating material, and flattening the stacking terminals while thinning the encapsulating material.

6. The method of claim 1, wherein said forming an encapsulating material is performed after said forming the respective stacking terminal on said each package substrate.

7. A method of manufacturing a semiconductor package, the method comprising:

attaching an array of package substrates to a carrier, a respective bottom side of each of the package substrates attached to a top side of the carrier, where each package substrate of the array of package substrates has passed testing prior to said attaching the array of package substrates, and each package substrate of the array of package substrates comprises a top side that comprises a die attach region;

for each package substrate of the array of package substrates, attaching a respective semiconductor die to the respective die attach region of said each package substrate;

for each package substrate of the array of package substrates, forming a respective stacking terminal on the respective top side of said each package substrate and outside of the respective die attach region of said each package substrate;

forming an encapsulating material that covers at least an upper side of each package substrate of the array of package substrates and at least a lateral side of each of the respective semiconductor dies; and

singulating package structures from the encapsulating material, the array of package substrates, the semiconductor dies, and the stacking terminals,

wherein prior to said singulating, the array of package substrates, the semiconductor dies, and the stacking terminals are encapsulated in the encapsulating material.

8. The method of claim 7, wherein said attaching a respective semiconductor die to the respective die attach region of said each package substrate comprises attaching the respective semiconductor die to the respective die attach region of said each package substrate while said each package substrate is attached to the carrier.

9. The method of claim 7, wherein said singulating package structures comprises singulating the package structures without cutting the encapsulated package substrates.

10. The method of claim 7, wherein the stacking terminals comprise copper.

11. The method of claim 7, comprising thinning the encapsulating material, and flattening the stacking terminals while thinning the encapsulating material.

12. The method of claim 11, wherein after said thinning the encapsulating material, the semiconductor dies remain covered by the encapsulating material.

13. The method of claim 7, wherein said forming an encapsulating material is performed after the forming of the stacking terminals.

14. A method of manufacturing a semiconductor package, the method comprising:

forming an array of package structures on a carrier, the array of package structures comprising;

an array of package substrates on the carrier, a respective bottom side of each of the package substrates coupled to a top side of the carrier, where each package substrate of the array of package substrates has passed testing prior to said forming the array of package substrates;

on a respective top side of each package substrate of the array of package substrates;

a respective semiconductor die coupled to the respective top side; and

a respective stacking terminal coupled to the respective top side and outside a lateral perimeter of the respective semiconductor die; and

an encapsulating material that encapsulates the array of package substrates, the semiconductor dies, and the stacking terminals; and

singulating package structures from the encapsulated array of package substrates, the semiconductor dies, and the stacking terminals.

15. The method of claim 14, wherein said forming the array of package structures on the carrier comprises coupling the respective semiconductor die to the respective top side of the respective package substrate while the respective package substrate is coupled to the carrier.

16. The method of claim 14, wherein said singulating package structures comprises singulating the package structures without cutting the encapsulated package substrates.

17. The method of claim 14, wherein said forming the array of package structures comprises thinning the encapsulating material, and flattening the stacking terminals while thinning the encapsulating material.

18. The method of claim 14, wherein said forming the array of package structures on the carrier comprises forming the encapsulating material after said stacking terminals have been formed.

19. The method of claim 14, wherein:

the array of package structures comprises an array of interposers on an upper side of the encapsulating material, wherein each interposer of the array of interposers is electrically connected to the respective stacking terminal of a respective package substrate of the array of package substrates; and

the encapsulating material encapsulates lateral sides of each package substrate of the array of package substrates.

20. The method of claim 19, wherein respective lateral sides of each interposer of the array of interposers are exposed from the encapsulating material.