Self-aligned tubular electrode portions inside memory openings for drain select gate electrodes in a three-dimensional memory device

• US 10,290,650 B1
• Filed: 02/05/2018
• Issued: 05/14/2019
• Est. Priority Date: 02/05/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Iwai, Takaaki
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US15/888,714
• Time in Patent Office: 463 Days
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7889 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 : characterised by the boundary region between the core and peripheral circuit regions

Abstract

Memory opening fill structures extend through an alternating stack of insulating layers and electrically conductive layers and a combination of an insulating fill material layer and plate electrode portions located over the alternating stack. Each memory opening fill structure includes a memory film, a vertical semiconductor channel laterally surrounded by the memory film, and a tubular electrode portion overlying the alternating stack and contacting a respective one of the plate electrode portions. The insulating fill material layer includes a drain select level isolation structure located between neighboring rows of memory opening fill structures. The plate electrode portions and the tubular electrode portions collectively constitute drain select gate electrodes. The tubular electrode portions are incorporated into a respective memory opening fill structure, and the drain select level isolation structure can be self-aligned to the memory opening fill structures.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate;

an insulating fill material layer and plate electrode portions located over the alternating stack;

memory openings vertically extending through the insulating fill material layer, the plate electrode portions, and the alternating stack, wherein the insulating fill material layer includes a drain select level isolation structure located between neighboring rows of memory openings, and wherein the drain select level isolation structure generally extends along a first horizontal direction; and

memory opening fill structures located in the memory openings, wherein each memory opening fill structure comprises a memory film, a vertical semiconductor channel laterally surrounded by the memory film, and a tubular electrode portion overlying the alternating stack and contacting a respective one of the plate electrode portions,

wherein the plate electrode portions and the tubular electrode portions collectively constitute drain select gate electrodes.

2. The three-dimensional memory device of claim 1, wherein:

the drain select level isolation structure includes a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions; and

each tubular electrode portion that is located within the neighboring rows of memory openings contacts the concave vertical sidewall portions of the drain select level isolation structure.

3. The three-dimensional memory device of claim 2, wherein:

each of the memory films is laterally indented inward at a level of the tubular electrode portions; and

an outer sidewall of each tubular electrode portion is vertically coincident with an outer sidewall of a memory film located within a same memory opening.

4. The three-dimensional memory device of claim 3, wherein the outer sidewall of each tubular electrode portion is vertically coincident with an overlying portion of the outer sidewall of the memory film located within the same memory opening, and with an underlying portion of the outer sidewall of the memory film located within the same memory opening.

5. The three-dimensional memory device of claim 2, wherein the concave vertical sidewall portions of the drain select level isolation structure contact convex vertical outer sidewalls of a subset of the tubular electrode portions and convex vertical outer sidewalls of a subset of the memory films.

6. The three-dimensional memory device of claim 1, wherein portions of the plate electrode portions that contact outer sidewalls of the tubular electrode portions comprise a different conductive material than the tubular electrode portions.

7. The three-dimensional memory device of claim 1, wherein the plate electrode portions have a different height than the tubular electrode portions.

8. The three-dimensional memory device of claim 1, wherein one of the vertical semiconductor channels has a lesser distance between an inner sidewall of the one of the vertical semiconductor channels and an outer sidewall of the one of the vertical semiconductor channels at a level of the tubular electrode portions than below the tubular electrode portions.

9. The three-dimensional memory device of claim 1, wherein:

the memory opening fill structures are arranged in multiple rows that extend along the first horizontal direction such that the rows are spaced apart along a second horizontal direction that is perpendicular to the first horizontal direction with a uniform inter-row pitch;

a first subset of the memory opening fill structures contacts the insulating fill material layer; and

a second subset of the memory opening fill structures does not contact the insulating fill material layer.

10. The three-dimensional memory device of claim 9, further comprising a contact level dielectric layer contacting top surfaces of the drain select gate electrodes, top surfaces of the memory opening fill structures, the planar vertical sidewall portions of the drain select level isolation structure, and convex vertical sidewalls of the memory opening fill structures.

11. The three-dimensional memory device of claim 1, wherein:

bottom surfaces of the tubular electrode portions are vertically offset from a horizontal plane including a bottom surface of the insulating fill material layer; and

the three-dimensional memory device further comprises drain regions contacting an upper end of a respective one of the vertical semiconductor channels and having a respective top surface within a same horizontal plane as a top surface of the insulating fill material layer.

12. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;

the substrate comprises a silicon substrate;

the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon;

the electrically conductive layers comprise a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate, and

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels.

13. A method of forming a three-dimensional memory device, comprising:

forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;

forming sacrificial matrices and an insulating fill material layer over the alternating stack;

forming memory openings through the sacrificial matrices, the insulating fill material layer, and the alternating stack;

forming tubular electrode portions in the memory openings;

forming memory stack structures within each memory opening and on a respective one of the tubular electrode portions, wherein each memory stack structure comprises a memory film and a vertical semiconductor channel; and

replacing the sacrificial matrices with plate electrode portions, wherein each contiguous combination of a plate electrode portion and a set of tubular electrode portions constitutes a drain select gate electrode.

14. The method of claim 13, wherein each of the tubular electrode portions is formed on a sidewall of a respective one of the memory openings, bottom surfaces of the tubular electrode portions are formed above a horizontal plane including a top surface of a topmost spacer material layer within the alternating stack, and top surfaces of the tubular electrode portions are formed below a horizontal plane including top surfaces of the sacrificial matrices.

15. The method of claim 13, wherein the memory openings are arranged as rows that extend along a first horizontal direction and a strip of the insulating fill material layer laterally extends between a neighboring pair of rows of the memory openings.

16. The method of claim 15, wherein:

the strip of the insulating fill material layer comprises a drain select level isolation structure which includes a first lengthwise sidewall and a second lengthwise sidewall that laterally extending along the first horizontal direction prior to formation of the memory openings;

a first row of memory openings within the neighboring pair of rows of memory openings is formed through the first lengthwise sidewall and does not intersect the second lengthwise sidewall;

a second row of memory openings with the neighboring pair of rows of memory openings is formed through the second lengthwise sidewall and does not intersect the first lengthwise sidewall;

the drain select level isolation structure includes a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions after formation of the memory openings; and

a subset of the tubular electrode portions is formed on the concave vertical sidewall portions of the drain select level isolation structure.

17. The method of claim 15, wherein:

the memory openings are arranged in multiple rows that are spaced apart along a second horizontal direction that is perpendicular to the first horizontal direction with a uniform inter-row pitch for an entirety of the group of memory stack structures; and

the tubular electrode portions are formed with a uniform lateral thickness.

18. The method of claim 13, further comprising:

forming first sacrificial fill material portions in the memory openings, wherein top surfaces of the first sacrificial fill material portions are located above a horizontal plane including a top surface of a topmost spacer material layer;

conformally depositing a conductive material layer on physically exposed portions of sidewalls of the memory openings and on top surfaces of the first sacrificial fill material portions;

forming the tubular electrode portions by anisotropically etching the conductive material layer;

forming second sacrificial fill material portions inside the tubular electrode portions, wherein top surfaces of the second sacrificial fill material portions are located below a horizontal plane including a top surface of the sacrificial matrices;

removing a top portion of each of the tubular electrode portions by etching portions of the tubular electrode portions that are not covered by the second sacrificial fill material portions; and

removing the second and first sacrificial fill material portions selective to the alternating stack and the tubular electrode portions.

19. The method of claim 13, wherein:

each memory film is formed on a respective one of the tubular electrode portions;

each vertical semiconductor channel is formed by depositing a semiconductor channel layer on the memory film and removing portions of the semiconductor channel layer from above the memory openings.

20. The method of claim 19, wherein:

each of the memory films comprises a lateral stack of a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer; and

the blocking dielectric layer is formed on a respective one of the tubular electrode portions and a respective sidewall portion of the insulating fill material layer.