Bitline settling improvement and FPN reduction by floating bitline during charge transfer
First Claim
1. A fast settling output line circuit, comprising:
- a photodiode (PD) adapted to accumulate image charges in response to incident light;
at least one transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from a TX receiving terminal of the TX transistor to the FD;
a reset (RST) transistor coupled to supply a reset FD voltage (VRFD) to the FD, wherein a reset (RST) gate voltage controls the RST transistor;
a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal;
a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor, and wherein the BLSN is coupled to a blacksun voltage generator; and
a current source generator coupled between the BLSN and a ground (AGND), wherein the current source generator provides adjustable current to the BLSN through a bias transistor controlled by a bias control voltage.
1 Assignment
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Accused Products
Abstract
A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.
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Citations
47 Claims
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1. A fast settling output line circuit, comprising:
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a photodiode (PD) adapted to accumulate image charges in response to incident light; at least one transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from a TX receiving terminal of the TX transistor to the FD; a reset (RST) transistor coupled to supply a reset FD voltage (VRFD) to the FD, wherein a reset (RST) gate voltage controls the RST transistor; a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal; a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor, and wherein the BLSN is coupled to a blacksun voltage generator; and a current source generator coupled between the BLSN and a ground (AGND), wherein the current source generator provides adjustable current to the BLSN through a bias transistor controlled by a bias control voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of fast settling an output line circuit, comprising:
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resetting a floating diffusion (FD) to a reset FD voltage (VRFD) by setting a reset (RST) gate voltage to high to switch on a reset (RST) transistor; precharging a bitline through a bitline parasitic capacitor to a SF source reset voltage by setting an idle enable voltage to high to turn on an idle enable transistor, when a row select (RS) transistor and a bitline enable transistor are switched off; precharging a bitline source node (BLSN) to a blacksun voltage by setting a blacksun enable voltage to high to turn on a blacksun enable transistor and by providing a blacksun control voltage to a blacksun transistor, and turning off a clamp enable transistor by setting a clamp enable voltage to low; discontinuing precharging to the bitline capacitor by setting the idle enable voltage to low to turn off the idle enable transistor; enabling a SF source terminal to the bitline and reconnecting the bitline to the BLSN by setting a RS gate voltage and a bitline enable voltage to high to close the RS transistor and the bitline enable transistor; disconnecting the FD from a pixel voltage (VPIX) by setting the RST gate voltage to low to switch off the RST transistor; and reading a background signal from the FD, wherein a SF transistor receives the background signal at a SF gate terminal and provides an amplified background signal at a SF source terminal, and wherein an ADC receives the amplified background signal from the bitline to an ADC input terminal. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. An imaging system with a fast settling output line circuit, comprising:
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a pixel array of pixel cells, wherein each pixel cell includes; a photodiode (PD) adapted to accumulate image charges in response to incident light; at least one transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from a TX receiving terminal of the TX transistor to the FD; a reset (RST) transistor coupled to supply a reset FD voltage (VRFD) to the FD, wherein a reset (RST) gate voltage controls the RST transistor; and a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal; a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor, and wherein the BLSN is coupled to a blacksun voltage generator; a current source generator coupled between the BLSN and a ground (AGND), wherein the current source generator provides adjustable current to the BLSN through a bias transistor controlled by a bias control voltage; a control circuitry coupled to the pixel array to control operation of the pixel array, wherein the control circuitry provides the TX gate voltage, the RST gate voltage, the RS gate voltage, the bitline enable voltage, a sample and hold (SH) voltage, a cascode voltage, a bias voltage, a clamp control voltage, a clamp enable voltage, a blacksun control voltage, a blacksun enable voltage, an idle control voltage (VIDLE), and an idle enable voltage to the pixel array; a readout circuitry coupled to the pixel array through a plurality of readout columns to readout image data from the plurality of pixels; and a function logic coupled to receive image data from the readout circuitry to store the image data from each one of the plurality of pixel cells, wherein the function logic provides instructions to the control circuitry. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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Specification