Bitline settling improvement and FPN reduction by floating bitline during charge transfer

• US 10,290,673 B1
• Filed: 12/22/2017
• Issued: 05/14/2019
• Est. Priority Date: 12/22/2017
• Status: Active Grant

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Inventors: Wang, Rui, Qu, Min, Ebihara, Hiroaki, Zhan, Zhiyong
• Primary Examiner(s): Vieaux, Gary C
• Application Number:
  US15/853,463
• Time in Patent Office: 508 Days
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 23/65 Control of camera operation in relation to power supply
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/627 Detection or reduction of inverted contrast or eclipsing effects
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

A photodiode is adapted to accumulate image charges in response to incident light. A transfer transistor is coupled between the photodiode and a floating diffusion to transfer the image charges from the photodiode to the floating diffusion. A transfer gate voltage controls the transmission of the image charges from a transfer receiving terminal of the transfer transistor to the floating diffusion. A reset transistor is coupled to supply a supply voltage to the floating diffusion. A source follower transistor is coupled to receive voltage of the floating diffusion from a gate terminal of the source follower and provide an amplified signal to a source terminal of the source follower. A row select transistor is coupled to enable the amplified signal from the SF source terminal and output the amplified signal to a bitline. A bitline enable transistor is coupled to link between the bitline and a bitline source node. The bitline source node is coupled to a blacksun voltage generator. A current source generator is coupled between the bitline source node and a ground. The current source generator provides adjustable current to the bitline source node through a bias transistor controlled by a bias control voltage.

Claims

1. A fast settling output line circuit, comprising:

a photodiode (PD) adapted to accumulate image charges in response to incident light;

at least one transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from a TX receiving terminal of the TX transistor to the FD;

a reset (RST) transistor coupled to supply a reset FD voltage (VRFD) to the FD, wherein a reset (RST) gate voltage controls the RST transistor;

a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal;

a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor, and wherein the BLSN is coupled to a blacksun voltage generator; and

a current source generator coupled between the BLSN and a ground (AGND), wherein the current source generator provides adjustable current to the BLSN through a bias transistor controlled by a bias control voltage.

2. The fast settling output line circuit of claim 1, further comprising a transfer storage (TS) transistor coupled between the PD and the TX transistor to transfer the image charges accumulated in the PD to the TX receiving terminal of the TX transistor, wherein a transfer storage gate (TSG) voltage controls the transfer storage (TS) transistor.

3. The fast settling output line circuit of claim 1, further comprising a row select (RS) transistor coupled between the SF source terminal and the bitline, wherein a row select (RS) gate voltage controls the RS transistor, and wherein the RS transistor passes the amplified signal from the SF source terminal to the bitline.

4. The fast settling output line circuit of claim 1, further comprising a row select (RS) transistor coupled between the SF drain terminal and a pixel voltage (VPIX), wherein a row select (RS) gate voltage controls the RS transistor, wherein the RS transistor passes the VPIX to the SF drain terminal, and wherein the SF source terminal connects to the bitline.

5. The fast settling output line circuit of claim 4, wherein the VPIX connects to a supply voltage AVDD.

6. The fast settling output line circuit of claim 4, wherein the VPIX connects to a regulated voltage supply, wherein the regulated voltage supply is regulated based on the AVDD.

7. The fast settling output line circuit of claim 4, wherein the VPIX and the VRFD have the same value.

8. The fast settling output line circuit of claim 4, wherein the VPIX and the VRFD have different values.

9. The fast settling output line circuit of claim 1, wherein the blacksun voltage generator is configured to receive the VPIX and provide an adjustable blacksun voltage to the BLSN, and wherein the blacksun voltage generator comprises:

a blacksun supply transistor receiving the VPIX and providing a blacksun supply voltage;

a blacksun transistor coupled to receive the blacksun supply voltage and provide an adjustable blacksun voltage controlled by a blacksun control voltage; and

a blacksun enable transistor coupled to pass the adjustable blacksun voltage to the BLSN controlled by a blacksun enable voltage.

10. The fast settling output line circuit of claim 9, further comprising a clamp voltage generator configured to connect to the BLSN.

11. The fast settling output line circuit of claim 10, wherein the clamp voltage generator is configured to receive the VPIX and provide an adjustable clamp voltage to the BLSN, and wherein the clamp voltage generator comprises:

a clamp transistor configured to receive the VPIX and provide an adjustable clamp voltage controlled by a clamp control voltage; and

a clamp enable transistor coupled to pass the adjustable clamp voltage to the BLSN controlled by a clamp enable voltage.

12. The fast settling output line circuit of claim 11, wherein the adjustable clamp voltage is lower than the adjustable blacksun voltage.

13. The fast settling output line circuit of claim 1, wherein a bias voltage provides the bias control voltage.

14. The fast settling output line circuit of claim 1, wherein the current source generator further comprises a cascode transistor coupled between the BLSN and the bias transistor controlled by a cascode control voltage.

15. The fast settling output line circuit of claim 14, wherein a cascode voltage provides the cascode control voltage.

16. The fast settling output line circuit of claim 14, wherein the current source generator further comprises:

a cascode sample and hold (SH) transistor coupled to receive the cascode voltage and provide the cascode control voltage controlled by a sample and hold (SH) voltage;

a bias sample and hold (SH) transistor coupled to receive the bias voltage and provide the bias control voltage controlled by the SH voltage;

a cascode hold capacitor coupled between the cascode control voltage and the AGND; and

a bias hold capacitor coupled between the bias control voltage and the AGND.

17. The fast settling output line circuit of claim 1, further comprising an idle voltage generator configured to receive the VPIX and provide an idle voltage to the bitline, wherein the idle voltage generator comprises:

an idle supply transistor configured to receive the VPIX and provide an idle supply voltage controlled by an idle control voltage (VIDLE); and

an idle enable transistor coupled to pass the idle supply voltage to the bitline controlled by an idle enable voltage.

18. The fast settling output line circuit of claim 1, further comprising a transmission gate passing the amplified signal from the bitline to an ADC input.

19. A method of fast settling an output line circuit, comprising:

resetting a floating diffusion (FD) to a reset FD voltage (VRFD) by setting a reset (RST) gate voltage to high to switch on a reset (RST) transistor;

precharging a bitline through a bitline parasitic capacitor to a SF source reset voltage by setting an idle enable voltage to high to turn on an idle enable transistor, when a row select (RS) transistor and a bitline enable transistor are switched off;

precharging a bitline source node (BLSN) to a blacksun voltage by setting a blacksun enable voltage to high to turn on a blacksun enable transistor and by providing a blacksun control voltage to a blacksun transistor, and turning off a clamp enable transistor by setting a clamp enable voltage to low;

discontinuing precharging to the bitline capacitor by setting the idle enable voltage to low to turn off the idle enable transistor;

enabling a SF source terminal to the bitline and reconnecting the bitline to the BLSN by setting a RS gate voltage and a bitline enable voltage to high to close the RS transistor and the bitline enable transistor;

disconnecting the FD from a pixel voltage (VPIX) by setting the RST gate voltage to low to switch off the RST transistor; and

reading a background signal from the FD, wherein a SF transistor receives the background signal at a SF gate terminal and provides an amplified background signal at a SF source terminal, and wherein an ADC receives the amplified background signal from the bitline to an ADC input terminal.

20. The method of claim 19, wherein the RS transistor passes the amplified background signal to the bitline when the RS transistor is closed by the RS gate voltage.

21. The method of claim 19, wherein the amplified background signal flows to the bitline.

22. The method of claim 19 further comprising:

precharging a cascode hold capacitor to a cascode voltage and a bias hold capacitor to a bias voltage by setting a sample and hold (SH) voltage to high to turn on a cascode SH transistor and a bias SH transistor; and

discontinuing precharging the cascode hold capacitor and the bias hold capacitor by setting a sample and hold (SH) voltage to low to turn off the cascode SH transistor and the bias SH transistor when turning off the idle enable transistor.

23. The method of claim 19 further comprising transferring image charges accumulated from the TX receiving terminal of the TX transistor to the FD by switching a transfer (TX) transistor on and off with a toggle of a TX gate voltage after the RS transistor and the bitline enable transistor are open by setting the RS gate voltage and the bitline enable to low.

24. The method of claim 23, wherein after the TX transistor is switched off by setting the TX gate voltage to low, the RS transistor and the bitline enable transistor are closed by setting the RS gate voltage and the bitline enable to high, and the blacksun enable transistor is turned off by setting the blacksun enable to low, and the clamp enable transistor is turned on by setting the clamp enable to high.

25. The method of claim 24, wherein the SF transistor amplifies the image charges from the TX receiving terminal of the TX transistor to an amplified image signal at a SF source terminal, and wherein the ADC receives the amplified image signal from the bitline to the ADC input terminal.

26. The method of claim 25, wherein the RS transistor passes the amplified image signal to the bitline when the RS transistor is closed by the RS gate voltage.

27. The method of claim 25, wherein the amplified image signal flows to the bitline.

28. The method of claim 19, wherein a transmission gate passes the amplified image signal from the bitline to the ADC input terminal by enabling the transmission gate.

29. The method of claim 19, wherein a voltage provided by the blacksun enable transistor is higher than a voltage provided by the clamp enable transistor to the BLSN.

30. The method of claim 19, wherein the SF source reset voltage is a voltage value of the SF source terminal when the FD is reset though the RST transistor to VRFD.

31. An imaging system with a fast settling output line circuit, comprising:

a pixel array of pixel cells, wherein each pixel cell includes;

a photodiode (PD) adapted to accumulate image charges in response to incident light;

at least one transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from a TX receiving terminal of the TX transistor to the FD;

a reset (RST) transistor coupled to supply a reset FD voltage (VRFD) to the FD, wherein a reset (RST) gate voltage controls the RST transistor; and

a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal;

a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor, and wherein the BLSN is coupled to a blacksun voltage generator;

a current source generator coupled between the BLSN and a ground (AGND), wherein the current source generator provides adjustable current to the BLSN through a bias transistor controlled by a bias control voltage;

a control circuitry coupled to the pixel array to control operation of the pixel array, wherein the control circuitry provides the TX gate voltage, the RST gate voltage, the RS gate voltage, the bitline enable voltage, a sample and hold (SH) voltage, a cascode voltage, a bias voltage, a clamp control voltage, a clamp enable voltage, a blacksun control voltage, a blacksun enable voltage, an idle control voltage (VIDLE), and an idle enable voltage to the pixel array;

a readout circuitry coupled to the pixel array through a plurality of readout columns to readout image data from the plurality of pixels; and

a function logic coupled to receive image data from the readout circuitry to store the image data from each one of the plurality of pixel cells, wherein the function logic provides instructions to the control circuitry.

32. The fast settling imaging system of claim 31, further comprising a transfer storage (TS) transistor coupled between the PD and the TX transistor to transfer the image charges accumulated in the PD to the TX receiving terminal of the TX transistor, wherein a transfer storage gate (TSG) voltage controls the TS transistor.

33. The fast settling imaging system of claim 31, further comprising a row select (RS) transistor coupled between the SF source terminal and the bitline, wherein a row select (RS) gate voltage controls the RS transistor, and wherein the RS transistor passes the amplified signal from the SF source terminal to the bitline.

34. The fast settling imaging system of claim 31, further comprising a row select (RS) transistor coupled between the SF drain terminal and a pixel voltage (VPIX), wherein a row select (RS) gate voltage controls the RS transistor, wherein the RS transistor passes the VPIX to the SF drain terminal, and wherein the SF source terminal connects to the bitline.

35. The fast settling imaging system of claim 34, wherein the VPIX connects to a supply voltage AVDD.

36. The fast settling imaging system of claim 34, wherein the VPIX connects to a regulated voltage supply, wherein the regulated voltage supply is regulated based on the AVDD.

37. The fast settling imaging system of claim 34, wherein the VPIX and the VRFD have the same value.

38. The fast settling imaging system of claim 34, wherein the VPIX and the VRFD have different values.

39. The fast settling imaging system of claim 35, further comprising a clamp voltage generator configured to connect to the bitline source node (BLSN).

40. The fast settling imaging system of claim 39, wherein the clamp voltage generator is configured to receive the VPIX and provide an adjustable clamp voltage to the BLSN, wherein the adjustable clamp voltage is lower than the adjustable blacksun voltage, and wherein the clamp voltage generator comprises:

a clamp transistor configured to receive the VPIX and provide an adjustable clamp voltage controlled by a clamp control voltage; and

a clamp enable transistor coupled to pass the adjustable clamp voltage to the BLSN controlled by a clamp enable voltage.

41. The fast settling imaging system of claim 31, wherein the blacksun voltage generator is configured to receive the VPIX and provide an adjustable blacksun voltage to the BLSN, and wherein the blacksun voltage generator comprises:

a blacksun supply transistor configured to receive the VPIX and provide a blacksun supply voltage;

a blacksun transistor coupled to receive the blacksun supply voltage and provide an adjustable blacksun voltage controlled by a blacksun control voltage; and

a blacksun enable transistor coupled to pass the adjustable blacksun voltage to the BLSN controlled by a blacksun enable voltage.

42. The fast settling imaging system of claim 31, wherein a bias voltage provides the bias control voltage.

43. The fast settling imaging system of claim 31, wherein the current source generator further comprises a cascode transistor coupled between the BLSN and the bias transistor controlled by a cascode control voltage.

44. The fast settling imaging system of claim 43, wherein a cascode voltage provides the cascode control voltage.

45. The fast settling imaging system of claim 43, wherein the current source generator further comprises:

a cascode sample and hold (SH) transistor coupled to receive the cascode voltage and provide the cascode control voltage controlled by the SH voltage;

a bias sample and hold (SH) transistor coupled to receive the bias voltage and provide the bias control voltage under the control of the SH voltage;

a cascode hold capacitor coupled between the cascode control voltage and the AGND; and

a bias hold capacitor coupled between the bias control voltage and the AGND.

46. The fast settling imaging system of claim 31, further comprising an idle voltage generator configured to receive the VPIX and provide an idle voltage to the bitline, wherein the idle voltage generator comprises:

an idle supply transistor configured to receive the VPIX and provide an idle supply voltage controlled by an idle control voltage (VIDLE); and

an idle enable transistor coupled to pass the idle supply voltage to the bitline controlled by an idle enable voltage.

47. The fast settling imaging system of claim 31, further comprising a transmission gate passing the amplified signal from the bitline to an ADC input.