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Bitline settling improvement and FPN reduction by floating bitline during charge transfer

  • US 10,290,673 B1
  • Filed: 12/22/2017
  • Issued: 05/14/2019
  • Est. Priority Date: 12/22/2017
  • Status: Active Grant
First Claim
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1. A fast settling output line circuit, comprising:

  • a photodiode (PD) adapted to accumulate image charges in response to incident light;

    at least one transfer (TX) transistor coupled between the PD and a floating diffusion (FD) to transfer the image charges from the PD to the floating diffusion (FD), wherein a transfer (TX) gate voltage controls the transmission of the image charges from a TX receiving terminal of the TX transistor to the FD;

    a reset (RST) transistor coupled to supply a reset FD voltage (VRFD) to the FD, wherein a reset (RST) gate voltage controls the RST transistor;

    a source follower (SF) transistor coupled to receive voltage of the FD from a SF gate terminal and provide an amplified signal to a SF source terminal;

    a bitline enable transistor coupled between a bitline and a bitline source node (BLSN), wherein a bitline enable voltage controls the bitline enable transistor, and wherein the BLSN is coupled to a blacksun voltage generator; and

    a current source generator coupled between the BLSN and a ground (AGND), wherein the current source generator provides adjustable current to the BLSN through a bias transistor controlled by a bias control voltage.

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