3D IC semiconductor device and structure with stacked memory
First Claim
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1. A 3D semiconductor device, the device comprising:
- first transistors;
second transistors, overlaying said first transistors;
third transistors, overlaying said second transistors; and
fourth transistors, overlaying said third transistors,wherein said second transistors, said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step,wherein at least one said third transistors comprises a source, channel, and drain, andwherein said source, said channel, and said drain have a similar doping type, andwherein at least one of said first transistors is part of a control circuit controlling at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors.
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Abstract
A 3D semiconductor device, the device including: first transistors; second transistors, overlaying the first transistors; third transistors, overlaying the second transistors; and fourth transistors, overlaying the third transistors, where the second transistors, the third transistors and the fourth transistors are self-aligned, being processed following the same lithography step, and where at least one of the first transistors is part of a control circuit controlling at least one of the second transistors, at least one of the third transistors and at least one of the fourth transistors.
852 Citations
20 Claims
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1. A 3D semiconductor device, the device comprising:
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first transistors; second transistors, overlaying said first transistors; third transistors, overlaying said second transistors; and fourth transistors, overlaying said third transistors, wherein said second transistors, said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step, wherein at least one said third transistors comprises a source, channel, and drain, and wherein said source, said channel, and said drain have a similar doping type, and wherein at least one of said first transistors is part of a control circuit controlling at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A 3D semiconductor device, the device comprising:
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first transistors; second memory cells, atop said first transistors; third memory cells, atop said second memory cells; and fourth memory cells, atop said third memory cells, wherein at least one of said second memory cells, at least one of said third memory cells and at least one of said fourth memory cells are self-aligned, being processed following the same lithography step, wherein said third memory cells comprise third transistors, wherein at least one of said third transistors comprises a source, channel, and drain, wherein said source, said channel, and said drain have a similar doping type, and wherein at least one of said first transistors is part of a control circuit, said control circuit controlling at least one of said second memory cells, at least one of said third memory cells and at least one of said fourth memory cells. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A 3D semiconductor device, the device comprising:
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first transistors; second transistors, overlaying said first transistors; third transistors, overlaying said second transistors; fourth transistors, overlaying said third transistors, wherein said second transistors, said third transistors and said fourth transistors are self-aligned, being processed following the same lithography step; and a memory peripheral circuit, wherein said memory peripheral circuit comprises at least one of said first transistors, and wherein said memory peripheral circuit controls at least one of said second transistors, at least one of said third transistors and at least one of said fourth transistors. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification
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Current AssigneeMonolithic 3D, Inc.
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Original AssigneeMonolithic 3D, Inc.
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InventorsSekar, Deepak C., Or-Bach, Zvi
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Primary Examiner(s)Nguyen, Duy T
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Application NumberUS15/803,732Publication NumberTime in Patent Office557 DaysField of Search257 5US Class CurrentCPC Class CodesH01L 2029/7857 of the accumulation typeH01L 21/268 using electromagnetic radia...H01L 21/6835 using temporarily an auxili...H01L 21/76254 with separation/delaminatio...H01L 21/8221 Three dimensional integrate...H01L 21/84 the substrate being other t...H01L 21/845 including field-effect tran...H01L 2221/6835 used as a support during bu...H01L 27/0688 Integrated circuits having ...H01L 27/105 including field-effect comp...H01L 27/1203 the substrate comprising an...H01L 27/1211 combined with field-effect ...H01L 29/42392 fully surrounding the chann...H01L 29/7841 with floating body, e.g. pr...H01L 29/785 having a channel with a hor...H10B 10/00 Static random access memory...H10B 12/056 the transistor being a FinFETH10B 12/20 DRAM devices comprising flo...H10B 12/36 the transistor being a FinFETH10B 12/50 Peripheral circuit region s...View All
