Semiconductor device and method for manufacturing the same

• US 10,290,715 B2
• Filed: 01/15/2018
• Issued: 05/14/2019
• Est. Priority Date: 01/23/2017
• Status: Active Grant

• Current Assignee: Hangzhou Silicon-Magic Semiconductor Technology Company Limited
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Cai, Jinyong, Liao, Zhongping
• Primary Examiner(s): Junge, Bryan R
• Application Number:
  US15/871,296
• Publication Number:
  US 20180212027A1
• Time in Patent Office: 484 Days
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device can include: a substrate having a semiconductor material; a plurality of semiconductor layers of a first conductivity type, and being sequentially stacked on the substrate, where a doping concentration of the semiconductor layers successively increases from bottom to top; a trench that extends from the surface of a topmost semiconductor layer into a bottommost semiconductor layer of the semiconductor layers; a plurality of field plates that correspond to the semiconductor layers, each field plate being located in a portion of the trench that corresponds to one of the semiconductor layers; and a trench pad located in a bottom and a sidewall of the trench, and being filled each space between two adjacent field plates, where the thickness of the trench pad between each field plate and corresponding semiconductor layer sequentially decreases from the bottom to the top.

Claims

1. A semiconductor device, comprising:

a) a substrate having a semiconductor material;

b) a plurality of semiconductor layers of a first conductivity type, and being sequentially stacked on said substrate, wherein a doping concentration of said plurality of semiconductor layers successively increases from bottom to top;

c) a trench that extends from the surface of a topmost semiconductor layer into a bottommost semiconductor layer of said plurality of semiconductor layers;

d) a plurality of field plates that correspond to said semiconductor layers, each field plate being located in a portion of said trench that corresponds to one of said plurality of semiconductor layers; and

e) a trench pad located in a bottom and a sidewall of said trench, and filling each space between two adjacent field plates, wherein the thickness of said trench pad between each field plate and corresponding semiconductor layer sequentially decreases from the bottom to the top, and wherein an electric field peak occurs between two adjacent of said plurality of field plates.

2. The semiconductor device of claim 1, further comprising:

a) a gate located on said plurality of field plates in said trench;

b) a body region with a second conductivity type, wherein said body region is located in said topmost semiconductor layer of said plurality of semiconductor layers, and separated by said trench;

c) a source region with a first conductivity type, wherein said source region is located in said body region and separated by said trench; and

d) a source electrode coupled to said source region, wherein said trench pad between said gate and said topmost semiconductor layer of said plurality of semiconductor layers is configured as a gate dielectric layer and an isolation dielectric layer of said semiconductor device, and said gate dielectric layer is located on said isolation dielectric layer.

3. The semiconductor device of claim 2, wherein said source electrode is coupled to each of said plurality of field plates.

4. The semiconductor device of claim 3, further comprising:

a) a body contact region with a second conductivity type located in said body region; and

b) a metal plug that couples said source electrode to said body contact region.

5. The semiconductor device of claim 1, wherein each semiconductor layer is depleted by a corresponding of said field plates and trench pads located therein.

6. The semiconductor device of claim 1, wherein said electric field peak is configured to increase an electric field of a drift region that comprises said plurality of semiconductor layers, and to lower an on-resistance of said semiconductor device.

7. The semiconductor device of claim 1, wherein said plurality of field plates are configured as polysilicon field plates.

8. The semiconductor device of claim 1, wherein said plurality of semiconductor layers are configured as epitaxial layers.

9. A method of manufacturing a semiconductor device, the method comprising:

a) forming a first epitaxial layer with a first conductivity type on a substrate of semiconductor material;

b) forming a second epitaxial layer with the first conductivity type on said first epitaxial layer, wherein the doping concentration of said first epitaxial layer is less than that of said second epitaxial layer;

c) forming a trench extending from the surface of said second epitaxial layer into said first epitaxial layer;

d) forming a trench pad in said trench;

e) disposing a first field plate in a portion of said trench located in said first epitaxial layer; and

f) disposing a second field plate in a portion of said trench located in said second epitaxial layer, wherein said trench pad is located on a sidewall and a bottom of said trench and fills a space between said first and second field plates, and the thickness of the trench pad between said first field plate and said first epitaxial layer is greater than that of the trench pad between said second field plate and said second epitaxial layer, wherein an electric field peak occurs between said first and second field plates.

10. The method of claim 9, further comprising:

a) forming a first oxide layer having a first thickness on a sidewall and a bottom of said trench;

b) depositing a first polysilicon layer in said trench having said first oxide layer;

c) etching said first polysilicon layer and said first oxide layer, wherein the remaining said first polysilicon layer is configured as said first field plate, and the remaining said first oxide layer is configured as a first portion of said trench pad;

d) depositing a second oxide layer having a second thickness on said first field plate, the first portion of said trench pad, and the sidewalls of said trench;

e) depositing a second polysilicon layer in said trench having said second oxide layer; and

f) etching said second polysilicon layer and said second oxide layer, wherein the remaining said second polysilicon is configured as said second field plate, and the remaining said second oxide layer is configured as a second portion of said trench pad.

11. The method of claim 10, further comprising:

a) depositing a third oxide layer on said second portion of said trench pad, said second field plate, and the sidewalls of said trench;

b) forming an isolation dielectric layer by chemical mechanical polishing and etching;

c) forming a fourth oxide layer on said isolation dielectric layer and the sidewalls of said trench;

d) depositing a third polysilicon layer in said trench with said fourth oxide layer; and

e) etching back said third polysilicon layer, wherein the remaining said third polysilicon layer is configured as a gate of said semiconductor device, and said fourth oxide layer is configured as a gate dielectric layer of said semiconductor device.

12. The method of claim 11, further comprising:

a) forming a body region with a second conductivity type in said second epitaxial layer located at both sides of said trench;

b) forming a source region with a first conductivity type in said body region located at both sides of said trench; and

c) forming a source electrode coupled to said source region and said first and second field plates.

13. The method of claim 12, further comprising:

a) forming a body contact region in said body region between formation of said source region and said source electrode; and

b) using a metal plug to couple said source electrode to said body contact region.