Semiconductor device and method for manufacturing the same

• US 10,290,720 B2
• Filed: 07/06/2017
• Issued: 05/14/2019
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Suzawa, Hideomi, Fujiki, Hiroshi, Godo, Hiromichi, Yamane, Yasumasa
• Primary Examiner(s): Vu, Vu A
• Application Number:
  US15/642,400
• Publication Number:
  US 20170309721A1
• Time in Patent Office: 677 Days
• Field of Search: 257 43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.

Claims

1. A semiconductor device comprising:

a first oxide layer over and in contact with an insulating surface;

a second oxide layer over and in contact with the first oxide layer;

a third oxide layer over and in contact with the second oxide layer;

an insulating layer over and in contact with the third oxide layer; and

a gate electrode over and in contact with the insulating layer,

wherein each of the first oxide layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,

wherein a thickness of the second oxide layer is larger than a thickness of the first oxide layer; and

wherein each of the first oxide layer and the third oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium, and an atomic ratio of gallium larger than the atomic ratio of zinc.

2. The semiconductor device according to claim 1, wherein the first oxide layer has a same atomic ratio of indium, gallium and zinc as the third oxide layer.

3. The semiconductor device according to claim 1, further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.

4. The semiconductor device according to claim 1, wherein the gate electrode is stacked layers, and one of the stacked layers includes at least one selected from an alloy of titanium and cobalt, an alloy of titanium and manganese, and an alloy of titanium and iron.

5. A semiconductor device comprising:

a first oxide layer over and in contact with an insulating surface;

a second oxide layer over and in contact with the first oxide layer;

a third oxide layer over and in contact with the second oxide layer;

an insulating layer over and in contact with the third oxide layer; and

a gate electrode over and in contact with the insulating layer,

wherein each of the first oxide layer, the second oxide layer and the third oxide layer contains indium, gallium and zinc,

wherein each of the first oxide layer and the third oxide layer has an atomic ratio of zinc larger than an atomic ratio of indium, and an atomic ratio of gallium larger than the atomic ratio of zinc, and

wherein the second oxide layer has an atomic ratio of indium larger than an atomic ratio of gallium and an atomic ratio of zinc.

6. The semiconductor device according to claim 5, wherein the first oxide layer has a same atomic ratio of indium, gallium and zinc as the third oxide layer.

7. The semiconductor device according to claim 5, further comprising a source electrode and a drain electrode interposed between a portion of the second oxide layer and a portion of the third oxide layer.

8. The semiconductor device according to claim 5, wherein the gate electrode is stacked layers, and one of the stacked layers includes at least one selected from an alloy of titanium and cobalt, an alloy of titanium and manganese, and an alloy of titanium and iron.

9. A semiconductor device comprising:

a first oxide layer comprising In, Ga and Zn;

a second oxide layer over and in contact with the first oxide layer, the second oxide layer being formed by an oxide target (In;

Ga;

Zn=1;

6;

4); and

a gate electrode that overlaps with the first oxide layer and the second oxide layer.

10. The semiconductor device according to claim 9, wherein the gate electrode is located over the second oxide layer.